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  "title": "HBM layer count and physical height",
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  "description": "Separate memory-die count, package thickness, stored bits and interface bandwidth.",
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  "revisionDate": "2026-10-07",
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  "topic": "Memory",
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      "id": "section-1",
      "title": "HBM layer count and physical height",
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      "title": "The mechanism",
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      "title": "Science and assumptions",
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      "id": "section-4",
      "title": "Stack-height budget",
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      "title": "Capacity is not bandwidth",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "A stack changes from 8 to 12 memory dies at unchanged external width and pin rate. What follows directly?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-stack-height-budget"
    },
    {
      "title": "SK hynix — the team behind 12-layer HBM3",
      "url": "https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/"
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    {
      "title": "Samsung — 36 GB HBM3E 12H development",
      "url": "https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram"
    },
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    {
      "title": "TSV formation, keep-out and backside reveal",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/"
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    {
      "title": "Temporary bonding, thinning and singulation",
      "url": "https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/"
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    {
      "title": "HBM heat, assembly yield and test access",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-thermal-yield/"
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    {
      "title": "Selecting a bonding route under constraints",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-bonding-process-selection/"
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    {
      "title": "HBM generations, channels, refresh and ECC",
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  "content": "Memory · Atlas v1.3.0\n\n# HBM layer count and physical height\n\nSeparate memory-die count, package thickness, stored bits and interface bandwidth.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-stack-height-budget)Die micrometers → assembled stack; vertical geometry exaggerated\n\nLearning objectiveSeparate memory-die count, package thickness, stored bits and interface bandwidth.\n\n## The mechanism\n\nAn HBM stack is assembled from separately fabricated DRAM dies and a base/interface structure. “12-high” describes a specified count of memory dies; it is neither twelve transistors nor a height in micrometers. Within a mechanical envelope, adding layers requires redistributing the thickness budget among silicon, inter-die joints, base structures and clearance. Wafer thinning and TSV reveal make vertical electrical paths accessible, but thin dies are harder to handle without bow or damage. Capacity rises with the number of usable bits in the memory dies. External bandwidth is set by the interface and achievable data rate, so more dies do not automatically create more external signal wires.\n\n1.  Begin with tested memory wafers and identify whether each drawing counts memory dies or the base die.\n2.  Thin on a compatible carrier; measure total thickness variation, warp and TSV reveal before handling the separated dies.\n3.  Allocate a mechanical budget to the base, every silicon layer, every counted bond line and the top allowance.\n4.  Verify that pad positions, channels, thermal path and package interfaces remain compatible as the layer count changes.\n5.  Test the assembled stack and report capacity, bandwidth and physical height as three separate outcomes.\n\n## Science and assumptions\n\n### Stack-height budget\n\n$$\nH=t_{\\mathrm{base}}+N t_{\\mathrm{die}}+J t_{\\mathrm{bond}}+t_{\\mathrm{cap}}\n$$\n\nH = tbase + N tdie + J tbond + tcap\n\nSymbols and units\n\nH\n\nModeled stack height\n\nµm\n\ntbase\n\nBase structure thickness\n\nµm\n\nN\n\nNumber of memory dies\n\ncount\n\ntdie\n\nMemory die thickness\n\nµm\n\nJ\n\nCounted bond lines\n\ncount\n\ntbond\n\nThickness per bond line\n\nµm\n\ntcap\n\nTop allowance in this model\n\nµm\n\nCount each physical thickness once. J includes every bond line represented in this cross-section; its value depends on whether the base interface is included.\n\nAssumptions Uniform die/bond thickness is a teaching simplification. Real layouts include local steps, tolerances and route-specific top structures.\n\n### Capacity is not bandwidth\n\n$$\nC=N C_{\\mathrm{die}},\\qquad B=\\frac{w r\\eta}{8}\n$$\n\nC = N Cdie; B = w r η / 8\n\nSymbols and units\n\nC\n\nStack capacity\n\nbytes\n\nCdie\n\nUsable capacity per memory die\n\nbytes\n\nw\n\nNumber of data bits transferred in parallel\n\nbits/transfer\n\nr\n\nTransfers per second per data pin\n\ntransfers/s\n\nη\n\nPayload efficiency\n\nfraction\n\nB\n\nUsable interface bandwidth\n\nbytes/s\n\nN\n\nNumber of memory dies\n\ncount\n\nCapacity C counts bytes; bandwidth B counts delivered bytes each second across the stated interface.\n\nAssumptions Equal capacity dies; data rate r already counts transfers; usable efficiency must be stated.\n\n## Engineering example\n\nSynthetic budget: base 60 µm, 12 memory dies × 30 µm, 12 included joints × 7 µm and a 40 µm allowance give 544 µm. Changing die thickness to 40 µm gives 664 µm. These are arithmetic inputs, not a JEDEC height limit or product cross-section.\n\n## Distinctions and tradeoffs\n\nDie count, silicon thickness and the external interface are separate design variables.\n\nThinner silicon frees vertical space while increasing handling sensitivity; smaller joints demand tighter assembly control.\n\nA larger working set can fit locally without a proportional increase in external memory bandwidth.\n\n## Specifications and interfaces\n\nLayer count\n\nMemory dies, separately from base\n\nRead each product drawing’s counting convention.\n\nHeight budget\n\nSilicon + joints + base + allowance\n\nA die-count label is not a dimensional drawing.\n\n### Interfaces\n\nTSV reveal Input\n\nExposed vertical conductors and measured silicon thickness\n\nAccelerator package Output\n\nStack height, interface footprint and thermal contact\n\n## Check your understanding\n\n### A stack changes from 8 to 12 memory dies at unchanged external width and pin rate. What follows directly?\n\n1.  Capacity can rise; external peak bandwidth need not change\n2.  External bandwidth must rise by 50%\n3.  Physical height must rise by 50%\n\nAnswer and reasoning\n\nCapacity can rise; external peak bandwidth need not change\n\nDie count, silicon thickness and the external interface are separate design variables.\n\n## Evidence and scope\n\nSK hynix’s 2023 account describes fitting more DRAM dies into the same height through thinner dies and changed assembly. The source supports the mechanism; the lab uses independent illustrative dimensions.\n\nAdjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.\n\n## Sources\n\n-   [SK hynix — the team behind 12-layer HBM3](https://news.skhynix.com/en/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3/)\n-   [Samsung — 36 GB HBM3E 12H development](https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-stack-height-budget-6372b6d7859deeb7.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [TSV formation, keep-out and backside reveal](https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/)\n-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)\n\n### Related lessons\n\n-   [HBM heat, assembly yield and test access](https://semiaifoundry.com/learn/atlas/hbm-stack-thermal-yield/)\n-   [Selecting a bonding route under constraints](https://semiaifoundry.com/learn/atlas/hbm-bonding-process-selection/)\n-   [HBM generations, channels, refresh and ECC](https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/)"
}