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  "id": "atlas-lesson-hbm-stack-assembly-test",
  "title": "HBM stack assembly, repair and staged test",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Combines screened memory dies into a delivered stack using a specified joining route.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Memory / HBM fabrication and assembly",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
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  "evidenceScope": "No vendor stack-yield, repair coverage or process recipe is asserted. Stack qualification and current volume status must be supported separately.",
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  "sections": [
    {
      "id": "section-1",
      "title": "HBM stack assembly, repair and staged test",
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      "id": "section-2",
      "title": "The mechanism",
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      "title": "Science and assumptions",
      "start": 1709,
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      "title": "Assembly-stage yield",
      "start": 1737,
      "end": 2685
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      "title": "Engineering example",
      "start": 2685,
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      "title": "Distinctions and tradeoffs",
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      "id": "section-7",
      "title": "Specifications and interfaces",
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      "title": "Interfaces",
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      "title": "Check your understanding",
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      "title": "What yield term belongs after an inventory of known-good dies has already been counted?",
      "start": 3858,
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      "title": "Evidence and scope",
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      "title": "Sources",
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      "id": "section-13",
      "title": "Continue exploring",
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      "id": "section-14",
      "title": "Foundations",
      "start": 5367,
      "end": 5712
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      "id": "section-15",
      "title": "Related lessons",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-stack-assembly-test"
    },
    {
      "title": "SK hynix — Small Size, Big Impact",
      "url": "https://news.skhynix.com/en/small-size-big-impact/"
    },
    {
      "title": "Advantest — Semiconductor test glossary",
      "url": "https://www.advantest.com/en/investors/ir-library/glossary/"
    },
    {
      "title": "DISCO — Tech Briefing 2023",
      "url": "https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf"
    },
    {
      "title": "Micron — HBM3E volume production begins",
      "url": "https://investors.micron.com/news/press-release/2024/Micron-Commences-Volume-Production-of-Industry-Leading-HBM3E-Solution-to-Accelerate-the-Growth-of-AI-02-26-2024/default.aspx"
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    {
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      "title": "Atlas releases and licensing",
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    {
      "title": "DFT, probe, binning and known-good die",
      "url": "https://semiaifoundry.com/learn/atlas/known-good-die-test/"
    },
    {
      "title": "Temporary bonding, thinning and singulation",
      "url": "https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/"
    },
    {
      "title": "TSV formation, keep-out and backside reveal",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/"
    },
    {
      "title": "Microbumps, reflow and thermocompression",
      "url": "https://semiaifoundry.com/learn/atlas/bump-thermocompression-assembly/"
    },
    {
      "title": "CoWoS-S and the silicon interposer route",
      "url": "https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/"
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  "content": "Memory / HBM fabrication and assembly · Atlas v1.3.0\n\n# HBM stack assembly, repair and staged test\n\nCombines screened memory dies into a delivered stack using a specified joining route.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-stack-assembly-test)DRAM cell to vertical stack; routes and logical mapping are separate\n\nLearning objectiveTrace a named HBM assembly route and place screening at valid population boundaries.\n\n## The mechanism\n\nAn HBM stack is assembled from memory dies that have already passed substantial wafer processing and screening. Thin dies are aligned and joined so vertical connections continue through the stack. SK hynix’s public MR-MUF description combines mass reflow joining with molded underfill; thermocompression-based flows use a different joining sequence and material arrangement. The atlas labels these alternatives instead of mixing their steps into one recipe. Testing can occur at die, partial-stack, completed-stack and final-package boundaries, with coverage shaped by available access. Qualification releases a product/process configuration; it is distinct from screening every stack produced on that route.\n\n1.  Select compatible screened dies and retain their identity and repair/bin status.\n2.  Align supported thin dies and establish vertical joint continuity using the named assembly route.\n3.  For the MR-MUF example, distinguish collective reflow from the subsequent protective molding/underfill role.\n4.  For a thermocompression alternative, preserve its actual joining and material sequence instead of borrowing MR-MUF order.\n5.  Perform the defined intermediate/final tests and count released stacks separately from qualification samples.\n\n## Science and assumptions\n\n### Assembly-stage yield\n\n$$\nN_{\\mathrm{out}}=N_{\\mathrm{ready}}\\prod_i y_i\n$$\n\nExpected output equals complete screened input sets times each successive stage’s conditional survival fraction.\n\nThe $y_{i}$ values are conditional on reaching each stage. The chain product does not itself require unconditional stage independence, but double-counted losses or unmodeled rework invalidate this simple path.\n\nSymbols and units\n\nN\\_out\n\nExpected surviving assembled outputs\n\nstacks\n\nN\\_ready\n\nComplete screened compatible input sets\n\nsets\n\nyᵢ\n\nConditional survival of the incoming population at new stage i\n\nfraction\n\ni\n\nOrdered assembly/test stage index\n\ninteger index\n\n$N_{\\mathrm{ready}}$ counts complete compatible input sets after screening; each $y_{i}$ is conditional survival through a new stage.\n\nAssumptions Stage factors require defined populations and nonoverlapping losses. Rework, repair and shared-cause failures need explicit branches.\n\n## Engineering example\n\nSynthetic inventory: 100 complete sets of screened dies encounter two new stages with 0.98 and 0.97 conditional survival. Expected output is 95.06 stacks before other losses, without reapplying original wafer yield.\n\n## Distinctions and tradeoffs\n\nMultiplying raw die yield through a stack of already screened dies double-counts losses and misstates incoming quality.\n\nEarlier test can avoid consuming good parts in a bad assembly but needs test access and adds handling/time; later test observes more completed interfaces.\n\nA logic die cannot become a memory-equipped accelerator until compatible good stacks are available in the required quantity.\n\n## Specifications and interfaces\n\nIncoming quality\n\nConditional quality after defined screening\n\nRaw DRAM wafer yield has already affected available die count.\n\nTest boundaries\n\nDie, stack and final package\n\nEach boundary adds or observes different failure opportunities.\n\n### Interfaces\n\nScreened thin dies and base Input\n\nKnown genealogy, compatible interfaces and assembly materials\n\nTested HBM stack Output\n\nDefined capacity, interface behavior and release status\n\n## Check your understanding\n\n### What yield term belongs after an inventory of known-good dies has already been counted?\n\n1.  An assumed perfect finished-stack yield\n2.  New assembly losses and residual conditional incoming defects\n3.  The same raw wafer yield applied again to every die\n\nAnswer and reasoning\n\nNew assembly losses and residual conditional incoming defects\n\nThe population at the input boundary determines which losses remain to be modeled.\n\n## Evidence and scope\n\nNo vendor stack-yield, repair coverage or process recipe is asserted. Stack qualification and current volume status must be supported separately.\n\nPropagate conditional assembly and final-test survival from already screened inputs; test coverage and common-cause failures require separate evidence.\n\n## Sources\n\n-   [SK hynix — Small Size, Big Impact](https://news.skhynix.com/en/small-size-big-impact/)\n-   [Advantest — Semiconductor test glossary](https://www.advantest.com/en/investors/ir-library/glossary/)\n-   [DISCO — Tech Briefing 2023](https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf)\n-   [Micron — HBM3E volume production begins](https://investors.micron.com/news/press-release/2024/Micron-Commences-Volume-Production-of-Industry-Leading-HBM3E-Solution-to-Accelerate-the-Growth-of-AI-02-26-2024/default.aspx)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-stack-assembly-test-bae6cef015ba73d2.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)\n-   [TSV formation, keep-out and backside reveal](https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/)\n\n### Related lessons\n\n-   [Microbumps, reflow and thermocompression](https://semiaifoundry.com/learn/atlas/bump-thermocompression-assembly/)\n-   [CoWoS-S and the silicon interposer route](https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/)"
}