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  "title": "HBM silicon intensity and allocation",
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  "description": "Estimates wafer demand per delivered bit without double-counting embedded yield losses.",
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  "revisionDate": "2026-10-07",
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  "topic": "Memory / HBM system constraints",
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  "version": "1.3.0",
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      "title": "HBM silicon intensity and allocation",
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      "title": "Two alternative demand models",
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      "title": "When is applying an extra stack-yield penalty to an empirical wafer/output-bit ratio justified?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-silicon-intensity"
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    {
      "title": "Micron — FY Q2 2024 prepared remarks, page 6",
      "url": "https://micron.gcs-web.com/static-files/1a8d6c22-3b89-4806-930c-d30cbcd270d5"
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    {
      "title": "SK hynix — TSMC collaboration on HBM",
      "url": "https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/"
    },
    {
      "title": "DISCO — Tech Briefing 2023",
      "url": "https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf"
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    {
      "title": "Micron — HBM3E",
      "url": "https://www.micron.com/products/memory/hbm/hbm3e"
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      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/hbm-silicon-intensity-ec1f2db8286d9d99.json"
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      "title": "Wafer maps and good-die yield",
      "url": "https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/"
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    {
      "title": "HBM stack assembly, repair and staged test",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/"
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    {
      "title": "HBM generations, channels, refresh and ECC",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/"
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    {
      "title": "Cycle time, ramp and effective capacity",
      "url": "https://semiaifoundry.com/learn/atlas/fab-ramp-cycle-time/"
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  "content": "Memory / HBM system constraints · Atlas v1.3.0\n\n# HBM silicon intensity and allocation\n\nEstimates wafer demand per delivered bit without double-counting embedded yield losses.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-silicon-intensity)Memory channels, package links and wafer-supply accounting\n\nLearning objectiveChoose a consistent HBM silicon-intensity method and avoid duplicated yield penalties.\n\n## The mechanism\n\nHBM requires silicon for memory arrays, peripheral circuits, vertical connections and base-die functions, followed by thinning, stacking and test. A stack’s footprint hides the area of its multiple dies. Silicon intensity can mean geometric area per bit or empirical wafer supply per delivered bit: different accounting methods. The geometric route explicitly applies relevant yields. An empirical ratio may already include those losses and must not receive them again. This lesson converts memory requirements into a consistent supply boundary with a dated supplier comparison whose denominator is kept explicit.\n\n1.  Specify gross, good-die, tested-stack or package-delivered bits as the output boundary.\n2.  For geometry, sum die area and apply explicitly defined, nonoverlapping yield losses.\n3.  For empirical intensity, determine which wafer-to-output losses the reported ratio already includes.\n4.  Calculate separate memory and base-die process demands without applying any loss twice.\n5.  Compare stack demand with logic, substrate and assembly constraints before predicting delivered accelerators.\n\n## Science and assumptions\n\n### Two alternative demand models\n\n$$\n\\begin{aligned}\\text{Geometric:}\\quad W&\\approx\\frac{B_{\\mathrm{target}}a_{\\mathrm{bit}}}{A_{\\mathrm{usable}}Y}\\\\\\text{Empirical:}\\quad W&=B_{\\mathrm{target}}I_{\\mathrm{emp}}\\end{aligned}\n$$\n\nThe geometric model divides target bits times gross area per bit by usable wafer area and an explicitly separate survival fraction. The alternative empirical model multiplies target output bits by measured wafers per output bit.\n\nThese are alternative models. An empirical output-bit intensity may already include yield; do not add the same loss again.\n\nSymbols and units\n\nW\n\nWafer requirement under the selected alternative model\n\nwafers\n\nB\\_target\n\nTarget delivered output bits\n\nbits\n\na\\_bit\n\nGross silicon area per bit under the geometric convention\n\nmm²/bit\n\nA\\_usable\n\nEffective usable area per wafer\n\nmm²/wafer\n\nY\n\nExplicit nonoverlapping survival fraction excluded from a\\_bit\n\nfraction\n\nI\\_emp\n\nEmpirical wafer requirement per delivered output bit\n\nwafers/output bit\n\n$B_{\\mathrm{target}}$ is target output bits, $a_{\\mathrm{bit}}$ gross silicon area/bit, $A_{\\mathrm{usable}}$ effective wafer area, Y the explicitly modeled nonoverlapping survival, and $I_{\\mathrm{emp}}$ wafers/output bit.\n\nAssumptions Account separately for packing, redundancy and logic-process base dies; do not combine these alternative formulas blindly.\n\n## Engineering example\n\nSynthetic empirical case: two wafer-equivalents per unit of tested-stack bits and ten units of demand require twenty wafer-equivalents. Applying a stack yield already embedded in that intensity would overstate demand.\n\n## Distinctions and tradeoffs\n\nWafer-supply intensity is neither package footprint nor a universal multiplier across HBM generations.\n\nMore capacity or bandwidth can consume additional wafer and assembly resources; architecture and memory-traffic improvements can reduce demand.\n\nHBM can limit deployable accelerators even when logic wafers are available, connecting model memory requirements to manufacturing allocation.\n\n## Specifications and interfaces\n\nGeometric method\n\nArea per gross bit plus explicit yields\n\nSeparate memory and logic-process base-die wafer requirements.\n\nEmpirical method\n\nWafer supply per delivered bit\n\nState generation, node, output boundary and included losses.\n\nDifferent quantities\n\nFootprint, summed silicon area and delivered capacity\n\nStack height and package area alone cannot measure wafer demand.\n\n### Interfaces\n\nMemory requirement and scoped model Input\n\nTarget bits, product configuration and nonoverlapping yield/intensity assumptions\n\nNormalized manufacturing demand Output\n\nWafer-equivalent or good-stack requirements over a stated period\n\n## Check your understanding\n\n### When is applying an extra stack-yield penalty to an empirical wafer/output-bit ratio justified?\n\n1.  Never for any geometric model either\n2.  Only when that ratio demonstrably excludes the stack loss\n3.  Always, because more factors improve accuracy\n\nAnswer and reasoning\n\nOnly when that ratio demonstrably excludes the stack loss\n\nThe starting metric’s denominator and included losses determine which additional factors are legitimate.\n\n## Evidence and scope\n\nMicron’s March 20, 2024 prepared remarks, page 6, report approximately 3× wafer supply for HBM3E versus DDR5 at equal bits and the same technology node. This historical supplier statement does not establish a universal generation-independent factor, package footprint or current customer allocation. The lab keeps synthetic inputs and does not add losses already embedded in an empirical ratio.\n\nCompare a synthetic geometric area ratio with an output-normalized supply ratio without applying the same yield loss twice.\n\n## Sources\n\n-   [Micron — FY Q2 2024 prepared remarks, page 6](https://micron.gcs-web.com/static-files/1a8d6c22-3b89-4806-930c-d30cbcd270d5)\n-   [SK hynix — TSMC collaboration on HBM](https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/)\n-   [DISCO — Tech Briefing 2023](https://disco.co.jp/jp/ir/movie/doc/E_Tech_Briefing_2023.pdf)\n-   [Micron — HBM3E](https://www.micron.com/products/memory/hbm/hbm3e)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-silicon-intensity-ec1f2db8286d9d99.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Wafer maps and good-die yield](https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/)\n-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)\n\n### Related lessons\n\n-   [HBM generations, channels, refresh and ECC](https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/)\n-   [Cycle time, ramp and effective capacity](https://semiaifoundry.com/learn/atlas/fab-ramp-cycle-time/)"
}