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  "title": "Selecting a bonding route under constraints",
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  "description": "Compare qualified output, height, thermal behavior, inspection and cost on the same product boundary.",
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  "revisionDate": "2026-10-07",
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      "title": "Selecting a bonding route under constraints",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-bonding-process-selection"
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    {
      "title": "Samsung — 36 GB HBM3E 12H development",
      "url": "https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram"
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    {
      "title": "SK hynix — Small Size, Big Impact",
      "url": "https://news.skhynix.com/en/small-size-big-impact/"
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    {
      "title": "imec — wafer-to-wafer hybrid bonding at 400 nm pitch",
      "url": "https://www.imec-int.com/en/articles/wafer-wafer-hybrid-bonding-pushing-boundaries-400nm-interconnect-pitch"
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      "title": "Mass reflow and molded underfill",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-mr-muf-route/"
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      "title": "HBM silicon intensity and allocation",
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  "content": "Packaging · Atlas v1.3.0\n\n# Selecting a bonding route under constraints\n\nCompare qualified output, height, thermal behavior, inspection and cost on the same product boundary.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-bonding-process-selection)Process-flow alternatives on a fixed stack/package boundary; schematic\n\nLearning objectiveCompare qualified output, height, thermal behavior, inspection and cost on the same product boundary.\n\n## The mechanism\n\nA useful process comparison starts from one required product: die count, footprint, electrical interfaces, operating conditions and test coverage. TC-NCF, MR-MUF and hybrid bonding organize joint formation and support differently. Each route moves effort among surface preparation, die placement, joint formation, encapsulation, annealing and inspection. “Finer pitch” and “faster bond tool” are individual attributes, not complete cost or delivery answers. Keep development readiness and demonstrated results beside each route, and leave supplier yield, process time or commercial price unknown when undisclosed.\n\n1.  Fix the same functional memory requirement and package-height boundary before comparing alternatives.\n2.  Map the chosen route’s preparation, handling, bonding/fill, thermal and test steps without replacing them with one generic bond operation.\n3.  Define compatible station capacity and conditional yield for the same input population.\n4.  Include consumables, equipment occupancy, inspection and losses in a cost per accepted stack model.\n5.  Reject or revise routes that miss electrical, thermal, mechanical or qualification requirements even if nominal throughput is high.\n\n## Science and assumptions\n\n### Cost per accepted stack\n\n$$\nc_{\\mathrm{good}}=\\frac{c_{\\mathrm{input}}+c_{\\mathrm{process}}+c_{\\mathrm{test}}}{Y}\n$$\n\ncgood = (cinput + cprocess + ctest) / Y\n\nSymbols and units\n\ncgood\n\nAverage modeled cost per accepted stack\n\ncurrency/stack\n\ncinput\n\nScreened components cost per starting set\n\ncurrency/set\n\ncprocess\n\nAssembly cost per starting set\n\ncurrency/set\n\nctest\n\nInspection/test cost per starting set\n\ncurrency/set\n\nY\n\nAccepted stacks per starting set\n\nfraction\n\nCosts are normalized to one assembled input set and divided by final pass fraction.\n\nAssumptions Simple no-rework average with all modeled costs incurred per input set; stage-dependent scrap/rework requires a yield waterfall.\n\n## Engineering example\n\nSynthetic routes: 100 currency units per input set at 90% final yield cost 111.1 per accepted stack. A 105-unit route at 97% costs 108.2. The example illustrates sensitivity; it ranks no commercial process.\n\n## Distinctions and tradeoffs\n\nA process must close the full product and production requirements; one favorable parameter does not establish a usable stack.\n\nReducing joint thickness can consume more surface-control effort; reducing bond time may expose inspection or supply as the next bottleneck.\n\nMemory economics and supply depend on accepted output from the complete route, affecting how many accelerators can be deployed.\n\n## Specifications and interfaces\n\nComparison basis\n\nSame product and test coverage\n\nDifferent layer counts or qualification stages are not an equal comparison.\n\nReadiness\n\nResearch, sample, qualified, production\n\nKeep date and measured scope visible.\n\n### Interfaces\n\nProcess candidate Input\n\nFlow, equipment and material requirements\n\nIntegration decision Output\n\nFeasible route plus remaining evidence needs\n\n## Check your understanding\n\n### Which comparison supports an engineering choice?\n\n1.  Same product boundary, yield denominator and qualification requirements\n2.  Only minimum reported pitch\n3.  Only the fastest advertised bonding operation\n\nAnswer and reasoning\n\nSame product boundary, yield denominator and qualification requirements\n\nA process must close the full product and production requirements; one favorable parameter does not establish a usable stack.\n\n## Evidence and scope\n\nRoute mechanisms are grounded in their named sources. Cost, cycle time and yield values in the workbench are transparent teaching scenarios, not supplier disclosures.\n\nAdjust stack layers, thickness, joint route, interface bandwidth and conditional yield; presets are synthetic, not supplier process windows.\n\n## Sources\n\n-   [Samsung — 36 GB HBM3E 12H development](https://news.samsung.com/global/samsung-develops-industry-first-36gb-hbm3e-12h-dram)\n-   [SK hynix — Small Size, Big Impact](https://news.skhynix.com/en/small-size-big-impact/)\n-   [imec — wafer-to-wafer hybrid bonding at 400 nm pitch](https://www.imec-int.com/en/articles/wafer-wafer-hybrid-bonding-pushing-boundaries-400nm-interconnect-pitch)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-bonding-process-selection-35150926514801ce.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Thermocompression with non-conductive film](https://semiaifoundry.com/learn/atlas/hbm-tc-ncf-route/)\n-   [Mass reflow and molded underfill](https://semiaifoundry.com/learn/atlas/hbm-mr-muf-route/)\n-   [Hybrid bonding: surface-to-interface closure](https://semiaifoundry.com/learn/atlas/hbm-hybrid-bond-route/)\n\n### Related lessons\n\n-   [HBM silicon intensity and allocation](https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/)\n-   [Compatible supply and converging bottlenecks](https://semiaifoundry.com/learn/atlas/compatible-supply-capacity/)\n-   [Package and system preserve the contract](https://semiaifoundry.com/learn/atlas/crg-package-system-closure/)"
}