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  "title": "Base die, PHY and memory controller",
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  "description": "Separates memory-stack logic from host scheduling and the electrical interface.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
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  "topic": "Memory / HBM system constraints",
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  "version": "1.3.0",
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      "title": "Base die, PHY and memory controller",
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      "title": "Interface timing budget",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "Which block principally chooses when queued host memory requests become DRAM commands?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#hbm-base-phy-controller"
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    {
      "title": "SK hynix — TSMC collaboration on HBM",
      "url": "https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/"
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      "title": "Synopsys — HBM3 Controller IP",
      "url": "https://www.synopsys.com/designware-ip/interface-ip/hbm/hbm3-controller.html"
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    {
      "title": "Synopsys — HBM4 PHY IP datasheet",
      "url": "https://www.synopsys.com/content/dam/synopsys/resources/dw/hbm4-phy-datasheet.pdf"
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      "title": "Atlas releases and licensing",
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    {
      "title": "HBM controller and PHY",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-controller/"
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      "title": "HBM stack assembly, repair and staged test",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/"
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    {
      "title": "DRAM cells, arrays and peripheral circuits",
      "url": "https://semiaifoundry.com/learn/atlas/dram-cell-array-fabrication/"
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    {
      "title": "HBM generations, channels, refresh and ECC",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/"
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    {
      "title": "CoWoS-S and the silicon interposer route",
      "url": "https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/"
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  "content": "Memory / HBM system constraints · Atlas v1.3.0\n\n# Base die, PHY and memory controller\n\nSeparates memory-stack logic from host scheduling and the electrical interface.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#hbm-base-phy-controller)Memory channels, package links and wafer-supply accounting\n\nLearning objectiveAssign controller, PHY, base-die and core-die functions to the correct boundaries.\n\n## The mechanism\n\nAn HBM connection has several cooperating control layers. DRAM core dies store and access data; a base die supports the stack’s interface and other generation-specific functions; the host memory controller schedules commands and manages access policy; the host PHY implements the physical signaling, timing and training boundary. These are not interchangeable objects. A base die fabricated on an advanced logic process does not automatically become the accelerator’s main memory controller. The chosen package route must connect compatible pad arrangements and electrical interfaces. This lesson follows one request across those boundaries and identifies which part owns scheduling, signal timing, vertical transport and storage.\n\n1.  Accept memory requests and map them to the controller’s address and scheduling policy.\n2.  Generate legal DRAM commands while coordinating refresh, ordering and data-integrity functions.\n3.  Pass the transaction across the defined controller/PHY interface.\n4.  Train and drive the physical link through the package and stack interface.\n5.  Return sensed data and handle reported errors within the stated host and memory responsibilities.\n\n## Science and assumptions\n\n### Interface timing budget\n\n$$\nT_{UI}=\\frac{1}{r},\\qquad m\\approx T_{UI}-t_{\\mathrm{uncertainty}}-t_{\\mathrm{required}}\n$$\n\nUnit interval is the reciprocal of the lane transfer rate. Timing margin is approximately that interval minus uncertainty and the required receiver window.\n\nSymbols and units\n\nT\\_UI\n\nUnit interval of the selected data-lane transfer convention\n\ns\n\nr\n\nEffective transfers per second on one data lane\n\ntransfers/s\n\nm\n\nRemaining timing margin\n\ns\n\nt\\_uncertainty\n\nBudgeted timing uncertainty\n\ns\n\nt\\_required\n\nRequired receiver timing window\n\ns\n\nData rate r uses transfers/s for one data lane and $T_{UI}$ seconds; other timing terms also use seconds.\n\nAssumptions Illustrative unit-interval budget. Exact setup/hold, jitter, skew and receiver models depend on the signaling standard and implementation.\n\n## Engineering example\n\nSynthetic link: 8×10⁹ transfers/s gives a 125 ps unit interval. A shorter interval tightens timing requirements even if the stored memory capacity is unchanged.\n\n## Distinctions and tradeoffs\n\nThe HBM base die is not automatically the host memory controller, and the PHY does not replace all scheduling logic.\n\nMore sophisticated scheduling or base-die functionality can improve efficiency and customization while adding area, verification and process dependencies.\n\nUsable HBM bandwidth depends on controllers, PHY timing, package connectivity and array behavior working together, not just memory pin count.\n\n## Specifications and interfaces\n\nHost boundary\n\nController ↔ PHY ↔ package link\n\nA defined digital-to-physical interface is required.\n\nStack boundary\n\nBase die ↔ DRAM core dies\n\nBase-die functions and fabrication process vary by generation/vendor.\n\n### Interfaces\n\nHost requests Input\n\nAddresses, data, ordering and service priorities\n\nHBM command/data link Output\n\nTrained electrical transactions compatible with the memory stack\n\n## Check your understanding\n\n### Which block principally chooses when queued host memory requests become DRAM commands?\n\n1.  A passive silicon TSV alone\n2.  The package lid\n3.  The memory controller\n\nAnswer and reasoning\n\nThe memory controller\n\nThe controller manages protocol and scheduling policy; the PHY realizes the physical signaling boundary.\n\n## Evidence and scope\n\nThe 2024 SK hynix–TSMC announcement describes a planned HBM4 base-die direction, not proof of its current production status. PHY-specific limits are not generalized to all HBM.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [SK hynix — TSMC collaboration on HBM](https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/)\n-   [Synopsys — HBM3 Controller IP](https://www.synopsys.com/designware-ip/interface-ip/hbm/hbm3-controller.html)\n-   [Synopsys — HBM4 PHY IP datasheet](https://www.synopsys.com/content/dam/synopsys/resources/dw/hbm4-phy-datasheet.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/hbm-base-phy-controller-50b2399bab56a4d7.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [HBM controller and PHY](https://semiaifoundry.com/learn/atlas/hbm-controller/)\n-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)\n\n### Related lessons\n\n-   [DRAM cells, arrays and peripheral circuits](https://semiaifoundry.com/learn/atlas/dram-cell-array-fabrication/)\n-   [HBM generations, channels, refresh and ECC](https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/)\n-   [CoWoS-S and the silicon interposer route](https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/)"
}