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  "title": "Grace Blackwell Superchip",
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  "description": "Couples one Grace CPU with two Blackwell GPUs so host and accelerator work can share a tightly integrated system.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "System integration",
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      "title": "Grace Blackwell Superchip",
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      "title": "Offload is useful only when saved compute exceeds movement cost",
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      "title": "Which description correctly separates the nested links?",
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      "title": "Continue exploring",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#grace-blackwell-superchip"
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    {
      "title": "NVIDIA: Blackwell platform announcement",
      "url": "https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing"
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    {
      "title": "NVIDIA GB200 NVL72 specifications",
      "url": "https://www.nvidia.com/en-us/data-center/gb200-nvl72/"
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    {
      "title": "NVIDIA: Inside Grace CPU architecture",
      "url": "https://developer.nvidia.com/blog/inside-nvidia-grace-cpu-nvidia-amps-up-superchip-engineering-for-hpc-and-ai/"
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    {
      "title": "NVIDIA CUDA Programming Guide: asynchronous data copies",
      "url": "https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/async-copies.html"
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    {
      "title": "Intel Advisor: Amdahl’s Law and measurement",
      "url": "https://www.intel.com/content/www/us/en/docs/advisor/user-guide/2024-2/use-amdahl-law.html"
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      "title": "Host CPU",
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    {
      "title": "GPU logic dies",
      "url": "https://semiaifoundry.com/learn/atlas/gpu-die/"
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      "title": "Grace LPDDR5X memory",
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      "title": "High-bandwidth memory stack",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack/"
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    {
      "title": "NVLink GPU interface",
      "url": "https://semiaifoundry.com/learn/atlas/nvlink-port/"
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  "content": "System integration · Atlas v1.3.0\n\n# Grace Blackwell Superchip\n\nCouples one Grace CPU with two Blackwell GPUs so host and accelerator work can share a tightly integrated system.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#grace-blackwell-superchip)Module-scale integration across several packages; schematic proportions\n\nLearning objectiveBudget compute, transfers and launch overhead for a CPU–GPU workload at a declared execution boundary.\n\n## The mechanism\n\nThe Grace Blackwell Superchip is a system integration unit, not one monolithic piece of silicon. It combines one CPU and two GPUs, with separate CPU memory and GPU HBM connected through a coherent interconnect. The GPUs also participate in a larger NVLink domain when installed in an NVL72 rack. This creates several nested scales: transistors form dies, dies and HBM form GPU packages, packages join the CPU in a module, and modules join a rack. The GPU’s internal die-to-die link, CPU–GPU coherence path and GPU-to-GPU scale-up communication serve different boundaries and cannot be treated as one interchangeable connection. This published reference explains a modern architecture; it is not evidence about the hardware used by any specific proprietary model service.\n\n1.  One Grace CPU prepares and coordinates work while its LPDDR memory holds host-side state.\n2.  Two Blackwell GPUs compute tensor operations using their local HBM, exchanging required information with the CPU over NVLink-C2C.\n3.  The GPUs connect into a larger NVLink scale-up domain, allowing multiple modules to cooperate on workloads that exceed one module.\n\n## Science and assumptions\n\n### Offload is useful only when saved compute exceeds movement cost\n\n$$\nT_{\\mathrm{GPU\\ path}}\\approx\\frac{F}{P_{\\mathrm{GPU}}}+\\frac{M_{\\mathrm{in}}}{B_{\\mathrm{in}}}+\\frac{M_{\\mathrm{out}}}{B_{\\mathrm{out}}}+T_{\\mathrm{launch}}\n$$\n\nSequential GPU-path time is arithmetic work divided by attained throughput, plus incoming transfer time, outgoing transfer time and launch overhead.\n\nSymbols and units\n\nT\\_GPU path\n\nSequential GPU execution-and-transfer time\n\ns\n\nF\n\nArithmetic work for the specified operation and format\n\noperations\n\nP\\_GPU\n\nAttained arithmetic throughput\n\noperations/s\n\nM\\_in\n\nBytes transferred into the device\n\nbytes\n\nB\\_in\n\nEffective incoming path bandwidth\n\nbytes/s\n\nM\\_out\n\nBytes transferred out of the device\n\nbytes\n\nB\\_out\n\nEffective outgoing path bandwidth\n\nbytes/s\n\nT\\_launch\n\nExposed launch overhead\n\ns\n\nF is operation count; PGPU is attained throughput; Min and Mout are transferred bytes; B values are effective one-direction path bandwidths. Compare the sum with the CPU execution time for the same operation. Reusing data already in HBM can remove repeated transfer terms, while coherent remote access still pays the relevant movement cost.\n\nAssumptions A sequential non-overlapped teaching model for a fixed workload and precision. Actual kernels may overlap transfers, hit caches, share memory coherently, or contend for bandwidth. Attained throughput and effective bandwidth must be measured rather than replaced blindly with product peaks.\n\n## Engineering example\n\nSynthetic non-overlapped job: 2 TFLOP at an attained 100 TFLOP/s takes 20 ms; 1 GB in and 0.5 GB out at 100 GB/s take 10 and 5 ms. Adding 0.1 ms dispatch gives 35.1 ms. This example uses invented attained rates, not product peaks.\n\n## Distinctions and tradeoffs\n\nSuperchip is a system-integration name, not proof of one monolithic die. Its CPU, GPUs, memories, and several different interconnects remain distinct physical components.\n\nTight integration can improve data movement and energy efficiency but ties the system to a particular memory and interconnect arrangement. Software must still place work and data carefully across the component boundaries.\n\nThis module joins general-purpose control with specialized matrix computation. Replicating and connecting it creates a larger platform for training and serving advanced models.\n\n## Specifications and interfaces\n\nProcessor composition\n\n1 Grace CPU + 2 Blackwell GPUs\n\nGB200 Superchip product configuration.\n\nGPU memory\n\n372 GB HBM3E, 16 TB/s aggregate\n\nCurrent official pair specification; distinct from B200 standalone variants.\n\nCPU–GPU link\n\n900 GB/s raw bidirectional NVLink-C2C\n\nCoherent interconnect, distinct from NVLink 5 and the internal GPU die link.\n\n### Interfaces\n\nHost preparation Input\n\nPrograms and CPU-resident data\n\nCoherent exchange Output\n\nCPU–GPU memory and control traffic\n\nRack fabric Output\n\nGPU tensors moving through NVLink scale-up links\n\n## Check your understanding\n\n### Which description correctly separates the nested links?\n\n1.  GPU internal die links, CPU–GPU C2C, and GPU scale-up NVLink serve different boundaries.\n2.  Every link in the module is the same kind of TSV.\n3.  The Ethernet NIC is the internal bridge between the two GPU logic dies.\n\nAnswer and reasoning\n\nGPU internal die links, CPU–GPU C2C, and GPU scale-up NVLink serve different boundaries.\n\nDifferent physical boundaries require different interfaces. Keeping these layers distinct explains how chips become modules and modules become larger machines.\n\n## Historical context\n\n### 2024 · Blackwell extends acceleration from multiple dies to rack-scale systems\n\nAnnounced on March 18, 2024, Blackwell joined two large logic dies within one GPU and paired new numerical formats with stronger GPU interconnect. Grace Blackwell systems brought CPU, GPU memory, scale-up networking, power, and cooling into a more tightly coordinated architecture; no specific proprietary model’s deployment is implied.\n\n[NVIDIA: Blackwell platform announcement](https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing)\n\n## Evidence and scope\n\nThe linked module sources establish CPU, GPU and memory boundaries. The calculation assumes serial phases and fixed precision; overlap, coherent accesses, caches and contention require a different execution model.\n\nFollow a modeled batched decode critical path and energy budget; prefill, expert routing and scheduling differences are comparison context rather than separately simulated algorithms.\n\n## Sources\n\n-   [NVIDIA GB200 NVL72 specifications](https://www.nvidia.com/en-us/data-center/gb200-nvl72/)\n-   [NVIDIA Blackwell platform announcement](https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing)\n-   [NVIDIA: Inside Grace CPU architecture](https://developer.nvidia.com/blog/inside-nvidia-grace-cpu-nvidia-amps-up-superchip-engineering-for-hpc-and-ai/)\n-   [NVIDIA CUDA Programming Guide: asynchronous data copies](https://docs.nvidia.com/cuda/cuda-programming-guide/04-special-topics/async-copies.html)\n-   [Intel Advisor: Amdahl’s Law and measurement](https://www.intel.com/content/www/us/en/docs/advisor/user-guide/2024-2/use-amdahl-law.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/grace-blackwell-superchip-b1d3ce602c66d4d5.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n-   [GPU logic dies](https://semiaifoundry.com/learn/atlas/gpu-die/)\n-   [Grace LPDDR5X memory](https://semiaifoundry.com/learn/atlas/lpddr-memory/)\n\n### Related lessons\n\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n-   [NVLink GPU interface](https://semiaifoundry.com/learn/atlas/nvlink-port/)\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)"
}