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  "title": "GPU logic dies",
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  "description": "Integrate transistor circuits into the compute, storage, and communication structures of one accelerator.",
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  "revisionDate": "2026-10-07",
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  "topic": "Advanced packaging",
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      "title": "GPU logic dies",
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      "title": "The mechanism",
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      "title": "Switching activity becomes heat",
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      "title": "Why use two large logic dies within one GPU?",
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      "title": "2024 · Blackwell extends acceleration from multiple dies to rack-scale systems",
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      "title": "Continue exploring",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#gpu-die"
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    {
      "title": "NVIDIA: Blackwell platform announcement",
      "url": "https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing"
    },
    {
      "title": "Texas Instruments: CMOS dynamic power",
      "url": "https://www.ti.com/lit/pdf/sprac07"
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      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/gpu-die-3a870139842fc285.json"
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      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Streaming multiprocessor",
      "url": "https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/"
    },
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      "title": "On-chip interconnect fabric",
      "url": "https://semiaifoundry.com/learn/atlas/on-chip-network/"
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      "title": "Thermal interface material",
      "url": "https://semiaifoundry.com/learn/atlas/thermal-interface/"
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      "title": "Grace Blackwell Superchip",
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  "content": "Advanced packaging · Atlas v1.3.0\n\n# GPU logic dies\n\nIntegrate transistor circuits into the compute, storage, and communication structures of one accelerator.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#gpu-die)Centimeter-scale logic dies; exact die dimensions not asserted\n\nLearning objectiveConnect switching activity to package-level heat.\n\n## The mechanism\n\nA logic die is a piece cut from a processed silicon wafer. Its surface carries layers of transistors and metal interconnect that implement arithmetic, memories, control, and interfaces. Datacenter Blackwell combines two large logic dies into one GPU, crossing the boundary with a dedicated high-bandwidth interface. This permits more circuitry than one exposure-sized die while preserving a single accelerator programming view. The package must connect those dies to each other, to memory stacks, and to power and cooling structures. Functional regions explain the die’s roles, but schematic proportions are not a verified proprietary floorplan. The die-to-die connection carries many parallel transfers, making package communication part of the architecture rather than merely a protective enclosure.\n\n1.  Wafer fabrication builds transistors and interconnect layers implementing logic, memory, control, and interfaces.\n2.  After testing and singulation, suitable dies are assembled with memory and dense interconnect structures into an accelerator package.\n3.  The packaged GPU receives instructions, data, power, and cooling, then repeatedly reuses its circuits for many software operations.\n\n## Science and assumptions\n\n### Switching activity becomes heat\n\n$$\nP_{\\mathrm{dynamic}}\\approx\\alpha C_{\\mathrm{switched}}V^2f\n$$\n\nDynamic power is approximately activity times switched capacitance times voltage squared times clock frequency.\n\nSymbols and units\n\nP\\_dynamic\n\nDynamic switching power\n\nW\n\nα\n\nEffective charging activity per clock period\n\nevents/cycle\n\nC\\_switched\n\nEffective switched capacitance\n\nF\n\nV\n\nSupply voltage\n\nV\n\nf\n\nClock frequency\n\ncycles/s\n\nα is the average charging activity per clock, Cswitched is effective switched capacitance, V is supply voltage, and f is clock frequency. Raising voltage has a quadratic effect in this model, while raising frequency has a linear effect. Consequently, adding transistors or increasing clocks does not provide free computation; energy-efficient architecture also reduces moved capacitance and unnecessary switching.\n\nAssumptions First-order CMOS capacitive switching model. Leakage, short-circuit current, clock networks, memory, I/O, and conversion losses contribute additional power; voltage and frequency are not independent across valid operating points. No Blackwell rail value is inferred.\n\n## Engineering example\n\nAt fixed capacitance and frequency, a 10% voltage increase raises the first-order dynamic term by about 21%, before leakage and regulator losses.\n\n## Distinctions and tradeoffs\n\nA Blackwell GPU’s 208 billion transistor count describes the combined two-die GPU, not 208 billion transistors in each die or each Superchip component.\n\nSplitting a large processor can extend integration beyond a single die limit, but adds package and communication demands. Yield, testing, routing, and heat must be solved together.\n\nThe die converts numerical instructions into physical switching activity. Its architecture determines how much useful matrix computation can be sustained for a given supply of data and power.\n\n## Specifications and interfaces\n\nIntegration\n\n2 large logic dies per GPU\n\nDatacenter Blackwell design described by NVIDIA.\n\nTransistor count\n\n208 billion per GPU\n\nCombined Blackwell GPU count, not a count for each die.\n\nDie-to-die link\n\n10 TB/s\n\nNVIDIA-reported interface bandwidth; do not relabel it NVLink.\n\n### Interfaces\n\nPower and clock Input\n\nSupply rails, timing, and control\n\nMemory and peer data Input\n\nHBM and adjacent-die transactions\n\nComputed results Output\n\nMemory stores and accelerator communication\n\n## Check your understanding\n\n### Why use two large logic dies within one GPU?\n\n1.  To give each model layer a permanent physical home.\n2.  To avoid needing any package wiring.\n3.  To integrate more circuitry than one exposure-sized logic die can provide.\n\nAnswer and reasoning\n\nTo integrate more circuitry than one exposure-sized logic die can provide.\n\nMultiple dies extend integration beyond a single die boundary, but require fast interconnect, advanced packaging, testing, and thermal management.\n\n## Historical context\n\n### 2024 · Blackwell extends acceleration from multiple dies to rack-scale systems\n\nAnnounced on March 18, 2024, Blackwell joined two large logic dies within one GPU and paired new numerical formats with stronger GPU interconnect. Grace Blackwell systems brought CPU, GPU memory, scale-up networking, power, and cooling into a more tightly coordinated architecture; no specific proprietary model’s deployment is implied.\n\n[NVIDIA: Blackwell platform announcement](https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing)\n\n## Evidence and scope\n\nThe model does not disclose or infer a specific GPU rail or Astra design.\n\nFollow a modeled batched decode critical path and energy budget; prefill, expert routing and scheduling differences are comparison context rather than separately simulated algorithms.\n\n## Sources\n\n-   [NVIDIA Blackwell platform announcement](https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing)\n-   [Texas Instruments: CMOS dynamic power](https://www.ti.com/lit/pdf/sprac07)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/gpu-die-3a870139842fc285.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Streaming multiprocessor](https://semiaifoundry.com/learn/atlas/streaming-multiprocessor/)\n-   [On-chip interconnect fabric](https://semiaifoundry.com/learn/atlas/on-chip-network/)\n\n### Related lessons\n\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n-   [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/)\n-   [Thermal interface material](https://semiaifoundry.com/learn/atlas/thermal-interface/)\n-   [Grace Blackwell Superchip](https://semiaifoundry.com/learn/atlas/grace-blackwell-superchip/)"
}