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  "title": "Metal gate and high-k dielectric",
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  "description": "Couples a control voltage into the channel while suppressing gate leakage.",
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  "revisionDate": "2026-10-07",
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  "topic": "Device physics",
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      "title": "Metal gate and high-k dielectric",
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      "title": "Why can a high-k gate dielectric help?",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#gate-stack"
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    {
      "title": "Intel — High-k and Metal Gate Research",
      "url": "https://www.intel.com/pressroom/kits/advancedtech/doodle/ref_HiK-MG/high-k.htm"
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    {
      "title": "Metal–oxide–semiconductor field-effect transistor",
      "url": "https://semiaifoundry.com/learn/atlas/mosfet/"
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      "title": "Insulators and low-k films",
      "url": "https://semiaifoundry.com/learn/atlas/dielectric/"
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  "content": "Device physics · Atlas v1.3.0\n\n# Metal gate and high-k dielectric\n\nCouples a control voltage into the channel while suppressing gate leakage.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#gate-stack)Nanometer-scale layered stack; layers expanded for visibility\n\nLearning objectiveExplain why equivalent oxide thickness is a stack property.\n\n## The mechanism\n\nThe gate stack contains a conducting electrode separated from the semiconductor by a thin dielectric system. It controls channel charge capacitively rather than requiring intentional conduction through the gate insulator. Making traditional silicon dioxide extremely thin improved control but increased tunneling leakage. High-k materials allow a physically thicker dielectric while preserving strong electrical coupling, and metal electrodes avoid the depletion associated with older polysilicon gates. The atlas lets the gate and dielectric peel apart to make their distinct roles clear. Effective oxide thickness is an electrical comparison, not necessarily the physical thickness of the complete stack. Actual material combinations and interfaces depend on a particular manufacturing process.\n\n1.  Place a conducting gate electrode across an insulating layer from the channel.\n2.  Apply a voltage so the stack capacitively changes channel charge.\n3.  Balance useful gate coupling with tunneling leakage, interface quality, and reliability.\n\n## Science and assumptions\n\n### Capacitance and equivalent oxide thickness\n\n$$\nC^{\\prime}=\\frac{\\varepsilon_0 k}{t},\\qquad \\mathrm{EOT}\\approx t_{\\mathrm{HK}}\\frac{k_{\\mathrm{SiO_2}}}{k_{\\mathrm{HK}}}\n$$\n\nCapacitance per area equals permittivity divided by thickness. Equivalent oxide thickness is high-k thickness times the silicon-dioxide to high-k permittivity ratio.\n\nSymbols and units\n\nC′\n\nDielectric capacitance per area\n\nF/m²\n\nε₀\n\nVacuum permittivity\n\nF/m\n\nk\n\nRelative permittivity of the layer\n\ndimensionless\n\nt\n\nPhysical layer thickness\n\nm\n\nEOT\n\nEquivalent silicon-dioxide thickness\n\nm\n\nt\\_HK\n\nPhysical high-k layer thickness\n\nm\n\nk\\_SiO₂\n\nRelative permittivity of silicon dioxide\n\ndimensionless\n\nk\\_HK\n\nRelative permittivity of the high-k layer\n\ndimensionless\n\nHigh permittivity permits a physically thicker dielectric with comparable electrical coupling. For several dielectric layers, inverse capacitances add, so interfacial films also matter.\n\nAssumptions Uniform linear dielectric layers in a series-capacitor approximation; ignores quantum capacitance and additional interface effects.\n\n## Engineering example\n\nA high-k film can be physically thicker than SiO₂ while giving a similar capacitance density; interface quality and leakage still matter.\n\n## Distinctions and tradeoffs\n\nEquivalent oxide thickness is an electrical comparison and need not equal the physical thickness of a high-k gate stack.\n\nStronger coupling improves control. Leakage, interface quality, and reliability limit aggressive dielectric scaling.\n\nEfficient switching helps fit more operations within a power budget. Gate-stack engineering supports that hardware efficiency.\n\n## Specifications and interfaces\n\nHigh-k example\n\nHafnium-based dielectric\n\nCommercial high-k/metal-gate introduction documented by Intel in 2007.\n\nUseful coupling\n\nCapacitance\n\nGate field controls channel charge.\n\nThickness distinction\n\nEOT ≠ physical stack thickness\n\nEquivalent oxide thickness is an electrical measure.\n\n### Interfaces\n\nGate signal Input\n\nElectrode voltage\n\nChannel field Output\n\nCapacitive electrostatic control\n\n## Check your understanding\n\n### Why can a high-k gate dielectric help?\n\n1.  It requires the gate to short into the channel\n2.  It can retain strong capacitive control with a physically thicker insulator\n3.  It removes every source of transistor leakage\n\nAnswer and reasoning\n\nIt can retain strong capacitive control with a physically thicker insulator\n\nHigher permittivity can preserve useful capacitance while easing the leakage problem of an extremely thin conventional dielectric.\n\n## Historical context\n\n### 2007 · High-k and metal gates enter Intel’s 45 nm generation\n\nHafnium-based dielectric and metal electrodes addressed leakage and gate-control limits of thinning silicon dioxide and polysilicon. The 45 nm name identifies the process generation.\n\n[Intel — High-k and Metal Gate Research](https://www.intel.com/pressroom/kits/advancedtech/doodle/ref_HiK-MG/high-k.htm)\n\n## Evidence and scope\n\nEOT is an electrostatic comparison, not a complete physical thickness specification.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [Intel — High-k and Metal Gate Transistor Research](https://www.intel.com/pressroom/kits/advancedtech/doodle/ref_HiK-MG/high-k.htm)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/gate-stack-70bfec722beb409b.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n-   [Insulators and low-k films](https://semiaifoundry.com/learn/atlas/dielectric/)\n\n### Related lessons\n\n-   [Controllable semiconductor channel](https://semiaifoundry.com/learn/atlas/channel/)\n-   [Gate-all-around nanosheet transistor](https://semiaifoundry.com/learn/atlas/gaa/)\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)"
}