# Gate-all-around nanosheet transistor Canonical: https://semiaifoundry.com/learn/atlas/gaa/ Revision: 2026-10-07 Rights: https://semiaifoundry.com/ai-atlas/licenses.html Device architectures · Atlas v1.3.0 # Gate-all-around nanosheet transistor Surrounds thin semiconductor sheets with a gate for stronger channel control. [Explore in Atlas](https://semiaifoundry.com/ai-atlas/#gaa)Nanometer-scale sheets; logical geometry, not vendor metrology Learning objectiveExplain why surrounding-gate geometry improves electrostatic control. ## The mechanism Gate-all-around devices place the gate around the channel perimeter. In a nanosheet implementation, several thin horizontal semiconductor sheets share source and drain regions while gate material wraps around each sheet. This differs from simply stacking complete independent transistors: the sheets form parallel conduction paths within one device. The atlas removes a section of the gate to expose the sheets and their connections. Width and stacking provide useful design freedom, but contacts, spacers, and material interfaces remain essential. RibbonFET is Intel's name for its gate-all-around implementation. The illustration is generic and does not claim to reproduce a proprietary production structure, exact sheet count, or vendor-specific dimensions. 1. Arrange thin semiconductor sheets between shared source and drain regions. 2. Surround the channel perimeter of each sheet with the controlling gate stack. 3. Combine their parallel conduction while accounting for spacers, contacts, and interfaces. ## Science and assumptions ### Nanosheet gated perimeter $$ W_{\mathrm{eff}}\approx2N_{\mathrm{sheet}}(W_{\mathrm{sheet}}+T_{\mathrm{sheet}}) $$ Total gated perimeter is approximately twice the sheet count times the sum of sheet width and thickness. Symbols and units W\_eff Total geometric gated perimeter nm N\_sheet Number of gated sheets count W\_sheet Rectangular sheet width nm T\_sheet Rectangular sheet thickness nm For rectangular sheets, the gate surrounds each perimeter. Several sheets add parallel controlled surfaces without representing several independent logical transistors. Assumptions Illustrative perimeter accounting for fully gated rectangular sheets; rounded corners, quantum confinement, and unequal surface transport alter actual electrical behavior. ## Engineering example For N sheets, the simple width estimate grows with each sheet perimeter; sheet release and conformal gate coverage become process gates. ## Distinctions and tradeoffs Several sheets in one GAA transistor are not automatically several independent transistors or processor layers. Wrapping the channel improves control. Complex interfaces and integration can limit the achievable benefit. GAA offers another route to efficient dense logic. It is an enabling device technology, not evidence that AGI has arrived. ## Specifications and interfaces Gate coverage Around the channel perimeter Shown as a cutaway to reveal the interior. Illustrated sheet count 3 conceptual sheets A teaching choice, not a vendor specification. Node name Technology-generation label Not the measured gate or sheet thickness. ### Interfaces Wrapped gate Input Electrostatic control around each sheet Shared source/drain Output Parallel channel currents ## Check your understanding ### What is shared by the sheets in the illustrated nanosheet device? 1. An independent software instruction per sheet 2. The source and drain regions of one transistor 3. A separate data-center network for each sheet Answer and reasoning The source and drain regions of one transistor The sheets represent parallel channels in one device. The three-sheet drawing is a teaching choice, not a vendor specification. ## Evidence and scope Nanosheet dimensions and route are representative; product-specific geometry is not inferred. Use the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism. ## Sources - [Intel Foundry — Advanced Process Technologies for Data Center](https://www.intel.com/content/www/us/en/foundry/library/advanced-process-technologies-for-data-center.html) - [Intel — Process Technology Naming](https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html) [Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/gaa-000ab4f62410b2a0.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html) ## Continue exploring ### Foundations - [Fin field-effect transistor](https://semiaifoundry.com/learn/atlas/finfet/) - [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/) ### Related lessons - [Gate sidewall and inner spacers](https://semiaifoundry.com/learn/atlas/spacer/) - [Source and drain regions](https://semiaifoundry.com/learn/atlas/source-drain/) - [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)