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  "id": "atlas-lesson-flipflop",
  "title": "Edge-triggered D flip-flop",
  "category": "learning",
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  "description": "Captures a bit at a clock event and retains it for the next computation stage.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Digital circuits",
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  "license": null,
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  "version": "1.3.0",
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      "title": "Edge-triggered D flip-flop",
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      "title": "The mechanism",
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      "title": "Setup-constrained clock period",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "What distinguishes a flip-flop from combinational logic?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#flipflop"
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    {
      "title": "MIT 6.111 — Sequential Logic and System Timing",
      "url": "https://ocw.mit.edu/courses/6-111-introductory-digital-systems-laboratory-spring-2006/31134a27ec1bedf570a26922790dfbec_lec11.pdf"
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    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Complementary CMOS inverter",
      "url": "https://semiaifoundry.com/learn/atlas/inverter/"
    },
    {
      "title": "Two-input CMOS NAND gate",
      "url": "https://semiaifoundry.com/learn/atlas/nand/"
    },
    {
      "title": "Clock tree and gated timing domains",
      "url": "https://semiaifoundry.com/learn/atlas/clock/"
    },
    {
      "title": "Full adder and carry network",
      "url": "https://semiaifoundry.com/learn/atlas/adder/"
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    {
      "title": "Multiply–accumulate and fused arithmetic",
      "url": "https://semiaifoundry.com/learn/atlas/mac/"
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    {
      "title": "Standard-cell library and physical design",
      "url": "https://semiaifoundry.com/learn/atlas/standard-cell/"
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  "content": "Digital circuits · Atlas v1.3.0\n\n# Edge-triggered D flip-flop\n\nCaptures a bit at a clock event and retains it for the next computation stage.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#flipflop)Microscopic sequential cell; timing diagram is conceptual\n\nLearning objectiveCombine register and logic delays into a setup timing budget while keeping hold checks separate.\n\n## The mechanism\n\nCombinational logic responds to its present inputs; sequential logic also carries state. A D flip-flop samples its data input around an active clock edge and holds the resulting output until a later capture. Internal feedback makes storage possible, while clock-controlled structures regulate when changes propagate. Data must satisfy setup and hold requirements, and the output appears after clock-to-output delay. These are physical timing constraints rather than perfectly instantaneous events. The atlas displays data, clock, and stored state separately so a viewer can watch an arithmetic result become the next stage's input. A register is a collection of such stored bits, often with additional enable and reset behavior.\n\n1.  Present stable data during the required interval around a capture edge.\n2.  Use clock-controlled internal structures to capture the state.\n3.  Hold the output through the next combinational evaluation until another permitted capture.\n\n## Science and assumptions\n\n### Setup-constrained clock period\n\n$$\nT_{\\mathrm{clock}}\\ge t_{CQ,\\max}+t_{\\mathrm{logic},\\max}+t_{\\mathrm{setup}}+t_{\\mathrm{uncertainty}}\n$$\n\nThe clock period must cover maximum clock-to-Q delay, maximum logic delay, setup time and the uncertainty budget.\n\nSymbols and units\n\nT\\_clock\n\nAvailable clock period\n\ns\n\nt\\_CQ,max\n\nMaximum launch register clock-to-Q delay\n\ns\n\nt\\_logic,max\n\nMaximum combinational path delay\n\ns\n\nt\\_setup\n\nCapture register setup time\n\ns\n\nt\\_uncertainty\n\nConservative nonnegative clock uncertainty budget\n\ns\n\nData must leave the first register, traverse combinational logic, and settle before the next capture. This sets a lower bound on the cycle time for a path.\n\nAssumptions Single-cycle synchronous path with conservative nonnegative clock uncertainty; hold constraints and multi-cycle exceptions are separate checks.\n\n## Engineering example\n\nSynthetic path: 40 ps clock-to-Q + 120 ps logic + 30 ps setup + 10 ps uncertainty requires a period of at least 200 ps. Its setup-only frequency ceiling is 1/(200 ps) = 5 GHz. A passing setup sum does not establish that the hold constraint passes.\n\n## Distinctions and tradeoffs\n\nA clock edge is not an infinitely precise instant with no constraints; setup, hold, and clock-to-output timing matter.\n\nMore pipeline stages can shorten combinational paths. Extra state and clock load consume area and power.\n\nFlip-flops coordinate arithmetic and control over time. They let many operations occupy different pipeline stages simultaneously.\n\n## Specifications and interfaces\n\nStored information\n\n1 bit\n\nAn elementary D flip-flop.\n\nCapture conditions\n\nSetup and hold\n\nInput timing requirements around the active edge.\n\nPipeline boundary\n\nClock-to-Q delay\n\nOutput does not change instantaneously.\n\n### Interfaces\n\nD and clock Input\n\nData and capture timing\n\nQ Output\n\nRetained state bit\n\n## Check your understanding\n\n### What distinguishes a flip-flop from combinational logic?\n\n1.  It computes without electrical power\n2.  It retains state between capture events\n3.  It contains no transistors\n\nAnswer and reasoning\n\nIt retains state between capture events\n\nStored state connects one stage of time to the next. Combinational logic instead derives outputs from its current inputs.\n\n## Evidence and scope\n\nThe timing budget follows the linked sequential-logic lecture. These are synthetic maximum-delay values for one synchronous path; clock skew, hold timing, variation and path exceptions need separate checks.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [MIT 6.111 — Sequential Logic and System Timing](https://ocw.mit.edu/courses/6-111-introductory-digital-systems-laboratory-spring-2006/31134a27ec1bedf570a26922790dfbec_lec11.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/flipflop-1f4567fc2c8b67fd.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Complementary CMOS inverter](https://semiaifoundry.com/learn/atlas/inverter/)\n-   [Two-input CMOS NAND gate](https://semiaifoundry.com/learn/atlas/nand/)\n\n### Related lessons\n\n-   [Clock tree and gated timing domains](https://semiaifoundry.com/learn/atlas/clock/)\n-   [Full adder and carry network](https://semiaifoundry.com/learn/atlas/adder/)\n-   [Multiply–accumulate and fused arithmetic](https://semiaifoundry.com/learn/atlas/mac/)\n-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)"
}