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  "id": "atlas-lesson-flip-chip-abf-substrate",
  "title": "Flip-chip assembly and organic substrates",
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  "format": "Atlas lesson",
  "description": "Connects face-down dies to a multilayer package substrate with a board-facing interface.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Packaging / Materials and assembly",
  "series": null,
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  "version": "1.3.0",
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  "sections": [
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      "id": "section-1",
      "title": "Flip-chip assembly and organic substrates",
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      "title": "Routing resource estimate",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "What role does the ABF material play inside a build-up substrate?",
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      "title": "Evidence and scope",
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      "title": "Continue exploring",
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      "title": "Foundations",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#flip-chip-abf-substrate"
    },
    {
      "title": "Amkor — Flip Chip Packaging",
      "url": "https://amkor.com/technology/flip-chip/"
    },
    {
      "title": "Ajinomoto — ABF materials business announcement",
      "url": "https://www.ajinomoto.co.jp/company/en/presscenter/press/detail/g2016_04_13.html"
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    {
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    {
      "title": "Package substrate",
      "url": "https://semiaifoundry.com/learn/atlas/package-substrate/"
    },
    {
      "title": "DFT, probe, binning and known-good die",
      "url": "https://semiaifoundry.com/learn/atlas/known-good-die-test/"
    },
    {
      "title": "Microbumps and bonding joints",
      "url": "https://semiaifoundry.com/learn/atlas/microbump/"
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    {
      "title": "Microbumps, reflow and thermocompression",
      "url": "https://semiaifoundry.com/learn/atlas/bump-thermocompression-assembly/"
    },
    {
      "title": "Underfill, warpage, thermal paths and qualification",
      "url": "https://semiaifoundry.com/learn/atlas/package-thermomechanical-reliability/"
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  "content": "Packaging / Materials and assembly · Atlas v1.3.0\n\n# Flip-chip assembly and organic substrates\n\nConnects face-down dies to a multilayer package substrate with a board-facing interface.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#flip-chip-abf-substrate)Die pads to package and board; routing pitch schematic\n\nLearning objectiveDistinguish flip-chip joints, substrate routing and ABF material roles.\n\n## The mechanism\n\nFlip-chip assembly places a die’s connection face toward its receiving structure, using an array of joints rather than only peripheral wires. An organic package substrate routes signals and power between fine die connections and larger board connections. Copper layers carry current; build-up dielectric materials such as ABF provide insulation and help enable multilayer routing. ABF is one material within the substrate, not the entire finished substrate or a substitute for a silicon interposer. Joint formation, underfill and later package construction introduce mechanical and thermal requirements that must be considered alongside the electrical routing diagram.\n\n1.  Fabricate and electrically inspect substrate routing, vias and connection sites.\n2.  Prepare die and receiver pad maps so their physical and electrical interfaces match.\n3.  Align and attach the die using the specified joint-formation route.\n4.  Add underfill or other support as required by the chosen assembly flow.\n5.  Complete external connections and test the packaged device under its defined conditions.\n\n## Science and assumptions\n\n### Routing resource estimate\n\n$$\nN_{\\mathrm{tracks}}\\approx\\frac{W_{\\mathrm{route}}}{p}\n$$\n\nA single-layer geometric track estimate divides available routing width by track pitch.\n\nSymbols and units\n\nN\\_tracks\n\nIdealized route-track count on one layer\n\ntracks\n\nW\\_route\n\nAvailable routing width\n\nμm\n\np\n\nTrack pitch\n\nμm\n\nAvailable routing width $W_{\\mathrm{route}}$ and track pitch p use matching length units; $N_{\\mathrm{tracks}}$ is an approximate count.\n\nAssumptions Single-layer geometric upper bound. Vias, return paths, keep-outs, escaping pads and design rules reduce usable routes.\n\n## Engineering example\n\nSynthetic routing corridor: 1 mm width at 20 μm track pitch suggests 50 geometric tracks on one layer before power/ground and escape constraints. It is not a real substrate design-rule capacity.\n\n## Distinctions and tradeoffs\n\nAn ABF supply statement is not a finished-substrate capacity statement; additional processing and qualification intervene.\n\nMore routing layers can support greater I/O demand while increasing substrate fabrication complexity and opportunities for defects.\n\nAccelerator packages must deliver high current and many signals through a manufacturable bridge between silicon and circuit board.\n\n## Specifications and interfaces\n\nSubstrate anatomy\n\nCopper, dielectrics, vias and external terminals\n\nABF denotes a build-up insulating material, not the complete stack.\n\nAssembly orientation\n\nDie connection face toward receiver\n\nA geometry definition, independent of a particular solder or bonding method.\n\n### Interfaces\n\nTested die and fabricated substrate Input\n\nCompatible pad maps, materials and incoming quality\n\nPackage-to-board interface Output\n\nRouted signals, power and mechanical attachment\n\n## Check your understanding\n\n### What role does the ABF material play inside a build-up substrate?\n\n1.  It replaces every conductor with memory cells\n2.  It insulates within a multilayer routing structure\n3.  It is the active GPU die\n\nAnswer and reasoning\n\nIt insulates within a multilayer routing structure\n\nThe substrate combines insulating and conducting features; no one resin film is the complete routed component.\n\n## Evidence and scope\n\nAssembly order is representative. Product-specific pad pitch, substrate stack-up, underfill and qualification limits remain undisclosed.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Amkor — Flip Chip Packaging](https://amkor.com/technology/flip-chip/)\n-   [Ajinomoto — ABF materials business announcement](https://www.ajinomoto.co.jp/company/en/presscenter/press/detail/g2016_04_13.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/flip-chip-abf-substrate-47ebe618c90dacb3.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Package substrate](https://semiaifoundry.com/learn/atlas/package-substrate/)\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n\n### Related lessons\n\n-   [Microbumps and bonding joints](https://semiaifoundry.com/learn/atlas/microbump/)\n-   [Microbumps, reflow and thermocompression](https://semiaifoundry.com/learn/atlas/bump-thermocompression-assembly/)\n-   [Underfill, warpage, thermal paths and qualification](https://semiaifoundry.com/learn/atlas/package-thermomechanical-reliability/)"
}
