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  "title": "Fin field-effect transistor",
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  "description": "Raises the channel into a fin so the gate controls multiple surfaces.",
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  "revisionDate": "2026-10-07",
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  "topic": "Device architectures",
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      "title": "Fin field-effect transistor",
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      "title": "What does the fin mainly improve?",
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      "title": "2011 · Intel announces 3D Tri-Gate for the 22 nm generation",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#finfet"
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    {
      "title": "Intel — Three-Dimensional Tri-Gate Announcement",
      "url": "https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure"
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    {
      "title": "Intel — Process Technology Naming",
      "url": "https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html"
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    {
      "title": "Original Device Study — Effective Fin Width and FinFET Geometry",
      "url": "https://www.mdpi.com/2079-9292/11/1/91"
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      "title": "Metal–oxide–semiconductor field-effect transistor",
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      "title": "Metal gate and high-k dielectric",
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    {
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      "title": "Gate-all-around nanosheet transistor",
      "url": "https://semiaifoundry.com/learn/atlas/gaa/"
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  "content": "Device architectures · Atlas v1.3.0\n\n# Fin field-effect transistor\n\nRaises the channel into a fin so the gate controls multiple surfaces.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#finfet)Nanometer-scale fin; node labels are technology names\n\nLearning objectiveCompare fin count and fin geometry as effective width.\n\n## The mechanism\n\nA FinFET lifts the semiconductor channel into a narrow vertical fin. In a common tri-gate realization, the gate crosses the fin and controls the two sidewalls and the top surface. That geometry gives stronger electrostatic control than a gate acting only from above a thick planar body. Adding fins can increase effective drive width, so the number and dimensions of fins become design choices rather than decorative repetition. The atlas compares a planar channel and fin channel at matched conceptual scale. It does not assign a modern process-node label to a measured gate length. The important visual change is how much of the conducting body lies close to a controlling gate.\n\n1.  Raise a thin semiconductor fin above its surroundings.\n2.  Wrap a common tri-gate around the fin’s top and two sides.\n3.  Use the closer gate coverage to improve control over channel conduction.\n\n## Science and assumptions\n\n### Effective gated width\n\n$$\nW_{\\mathrm{eff}}\\approx N_{\\mathrm{fin}}(2H_{\\mathrm{fin}}+W_{\\mathrm{fin}})\n$$\n\nEffective tri-gate width is approximately fin count times twice the fin height plus its top width.\n\nSymbols and units\n\nW\\_eff\n\nTotal geometric gated width\n\nnm\n\nN\\_fin\n\nNumber of fins\n\ncount\n\nH\\_fin\n\nGated fin sidewall height\n\nnm\n\nW\\_fin\n\nGated fin top width\n\nnm\n\nA tri-gated rectangular fin contributes two sidewall heights and its top width. Multiple fins add parallel gated perimeter, explaining discrete drive-width choices.\n\nAssumptions Geometric approximation for a tri-gate with comparable surface conduction; double-gate devices and real mobility/corner effects differ.\n\n## Engineering example\n\nAdding one identical fin increases the idealized effective width by roughly 2H\\_fin+$W_{\\mathrm{fin}}$; variability and quantized layout remain.\n\n## Distinctions and tradeoffs\n\nA FinFET’s multiple controlled surfaces do not mean it has three independent logical gates.\n\nThree-dimensional control helps suppress leakage. Fin geometry constrains drive choices and manufacturing tolerances.\n\nFinFETs enabled dense CMOS generations used in accelerators. They improve the physical switches beneath software-level parallelism.\n\n## Specifications and interfaces\n\nCommon gate coverage\n\nTwo sides plus top\n\nTri-gate FinFET example; other multigate variants exist.\n\nWidth control\n\nFin count and dimensions\n\nDiscrete fins affect available drive strength.\n\nHistorical milestone\n\nIntel announcement, 2011\n\n22 nm process generation; node name is not a scale ruler.\n\n### Interfaces\n\nGate voltage Input\n\nField over multiple channel surfaces\n\nFin channel Output\n\nControlled source–drain conduction\n\n## Check your understanding\n\n### What does the fin mainly improve?\n\n1.  Electrostatic gate control over the channel body\n2.  The number of software layers in the model\n3.  The accuracy of a neural network without training\n\nAnswer and reasoning\n\nElectrostatic gate control over the channel body\n\nFin geometry places more of the channel close to the gate. Any AI benefit arises through circuit-level hardware performance.\n\n## Historical context\n\n### 2011 · Intel announces 3D Tri-Gate for the 22 nm generation\n\nMultisurface gate control moved a major production logic platform beyond planar transistor geometry. This is an Intel commercialization milestone, not the first invention of every FinFET concept.\n\n[Intel — Three-Dimensional Tri-Gate Announcement](https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure)\n\n## Evidence and scope\n\nThe expression omits fin corners, mobility variation, parasitic resistance and layout rules.\n\nUse the switching investigation to connect physical charge, circuit load and arithmetic; the numerical library has no standalone model of this lesson’s full mechanism.\n\n## Sources\n\n-   [Intel — Three-Dimensional Tri-Gate Transistors, 2011](https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure)\n-   [Intel — Process Technology Naming](https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html)\n-   [Original Device Study — Effective Fin Width and FinFET Geometry](https://www.mdpi.com/2079-9292/11/1/91)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/finfet-bc5fd21dcd81b635.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n-   [Metal gate and high-k dielectric](https://semiaifoundry.com/learn/atlas/gate-stack/)\n\n### Related lessons\n\n-   [Controllable semiconductor channel](https://semiaifoundry.com/learn/atlas/channel/)\n-   [Gate-all-around nanosheet transistor](https://semiaifoundry.com/learn/atlas/gaa/)\n-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)"
}