# How a FinFET fin is formed and integrated

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Revision: 2026-10-07
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Fabrication / FEOL and MOL · Atlas v1.3.0

# How a FinFET fin is formed and integrated

Turns a three-dimensional silicon ridge into a controlled transistor channel.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#fin-formation-integration)Nanometer device cross-sections; reference flow with alternatives

Learning objectiveConnect fin formation and isolation recess to a FinFET’s controlled surfaces.

## The mechanism

A FinFET obtains stronger gate control by placing the gate around multiple sides of a narrow silicon fin. The device geometry must be manufactured before it can provide that advantage. Patterning defines the fin location; etching establishes height and sidewalls; isolation fill and recess expose the intended channel portion. Gate and source/drain modules then complete a transistor around the preserved fin. Width, height, roughness and stress all matter, and their influence differs from simply drawing a narrower planar channel. The lesson follows one fin through the sequence so that isolated process steps remain connected to the final electrical path.

1.  Pattern the fin arrangement using the chosen lithography and pattern-transfer route.
2.  Etch the semiconductor to establish fin height and sidewall profile.
3.  Fill surrounding isolation and recess it to expose the desired channel surfaces.
4.  Form the gate module around the accessible fin surfaces and integrate spacers and source/drain regions.
5.  Measure fin geometry and completed-device behavior to connect structural variation with electrical results.

## Science and assumptions

### Geometric effective-width estimate

$$
W_{\mathrm{eff}}\approx N_f(2H_f+W_f)
$$

Effective gated width is approximately fin count times twice exposed height plus top width.

Symbols and units

W\_eff

Geometric effective gated width

nm

N\_f

Fin count

count

H\_f

Exposed gated fin height

nm

W\_f

Gated fin top width

nm

Fin count $N_{f}$ is dimensionless; exposed fin height $H_{f}$ and top width $W_{f}$ use length units.

Assumptions A tri-gate geometric approximation. Different surface mobilities, corner effects and electrostatics prevent exact current prediction from perimeter alone.

## Engineering example

Synthetic geometry: two fins with $H_{f} = 30$ nm and $W_{f} = 8$ nm give a perimeter estimate of 136 nm. This is effective gated width, not the cell footprint or a measured current.

## Distinctions and tradeoffs

A process node name does not specify the fin width, and fin width alone does not determine transistor drive.

Taller or narrower fins can improve density or electrostatics while increasing etch, variability and mechanical integration demands.

FinFET manufacturing enabled dense high-performance logic used across processors and accelerators; process variation changes usable frequency and leakage bins.

## Specifications and interfaces

Channel geometry

Fin height, width and exposed sidewalls

Dimensions refer to named material boundaries after defined steps.

Width control

Integer fin count in many designs

Effective drive width and physical layout width are different quantities.

### Interfaces

Patterned active region Input

Fin position and surrounding isolation plan

Fin channel Output

Three-dimensional semiconductor body ready for gate integration

## Check your understanding

### Why does fin-height variation matter even if the top-view linewidth is correct?

1.  It changes the gate-controlled channel perimeter and integration geometry
2.  Only top-view dimensions affect a FinFET
3.  It changes silicon into copper

Answer and reasoning

It changes the gate-controlled channel perimeter and integration geometry

Current can flow along multiple gated surfaces, so a two-dimensional top view is incomplete.

## Evidence and scope

Sequence is representative. Fin counts, dimensions and material recipes are illustrative, with no claim about a particular production node.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Applied Materials — New Ways to Shrink](https://ir.appliedmaterials.com/static-files/f2fbf48d-a761-4c4f-ab4c-73f312ab1ebc)
-   [MIT 6.152J — Micro/Nano Processing Technology lecture notes](https://ocw.mit.edu/courses/6-152j-micro-nano-processing-technology-fall-2005/pages/lecture-notes/)
-   [Intel — Reinvents Transistors Using New 3-D Structure](https://www.intc.com/news-events/press-releases/detail/655/intel-reinvents-transistors-using-new-3-d-structure)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/fin-formation-integration-9fa2751fa526e028.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Fin field-effect transistor](https://semiaifoundry.com/learn/atlas/finfet/)
-   [Plasma and wet etch: selectivity and profile](https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/)

### Related lessons

-   [Wells and shallow trench isolation](https://semiaifoundry.com/learn/atlas/wells-isolation-integration/)
-   [Source/drain, spacers, contacts and MOL](https://semiaifoundry.com/learn/atlas/source-drain-contact-integration/)