# Cycle time, ramp and effective capacity

Canonical: https://semiaifoundry.com/learn/atlas/fab-ramp-cycle-time/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Fabrication / Control, test and ramp · Atlas v1.3.0

# Cycle time, ramp and effective capacity

Connects tool throughput, queues, qualification and yield learning over time.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#fab-ramp-cycle-time)Feature measurements, wafer maps and time-dependent production

Learning objectiveInterpret time-dependent manufacturing capacity without confusing starts and released output.

## The mechanism

A factory’s output changes during ramp. Equipment is installed and qualified, process capability stabilizes, staffing and maintenance practices mature, and product yield evolves. Nameplate tool throughput describes only part of that path. Re-entrant processing and shared bottlenecks create waiting time between operations, while engineering holds and qualification gates can stop release. Wafer starts, work in process and good dies shipped are therefore different time-series quantities. The lesson follows a batch through a simple factory and asks which constraint determines completed output today, then separates announced future capacity from operating and product-qualified capacity.

1.  Separate installed equipment from capacity qualified for the intended product route.
2.  Convert repeated tool visits and shared product demand to a consistent load basis.
3.  Track work-in-process, queues, holds and departures over time.
4.  Combine throughput with measured release yield using nonoverlapping denominators.
5.  Update the binding constraint as tools, yields or downstream assembly readiness change.

## Science and assumptions

### Little’s law

$$
\mathrm{WIP}=X\,T_{\mathrm{cycle}}
$$

For stable flow, average work in process equals throughput times mean cycle time.

Symbols and units

WIP

Average work-in-process inventory

declared material units

X

Stable throughput through the same boundary

material units/day

T\_cycle

Mean cycle time through that boundary

days

WIP counts a consistent unit, throughput uses units/day and cycle time days, averaged over the same stable system.

Assumptions Long-run stable flow with consistent boundaries. During ramp or a growing backlog, transient accounting is needed instead of naïve steady-state inference.

## Engineering example

Synthetic stable line: 500 wafers of WIP and 10 wafers/day throughput imply 50 days average cycle time. The equation does not prove a newly ramping line is already stable.

## Distinctions and tradeoffs

A capacity announcement or a tool’s rated wafers/hour is not equivalent to good dies shipped per month.

Running near full utilization can build queues and increase cycle time; spare capacity can absorb variation but costs money.

The synchronization of good logic dies, HBM, substrates and package capacity determines when accelerator demand can become delivered hardware.

## Specifications and interfaces

Flow metrics

Starts, WIP, throughput and cycle time

Use a common material boundary and calendar interval.

Capacity state

Installed → qualified → producing → released

Each transition requires evidence; dates can differ.

### Interfaces

Qualified routes and resources Input

Tools, utilities, materials, labor and release criteria

Released output Output

Good units available after their actual process and test history

## Check your understanding

### What happens if wafer starts rise while the final qualified bottleneck throughput stays fixed?

1.  WIP and cycle time can rise without more completed output
2.  Good output must rise in exact proportion
3.  Every wafer instantly becomes a package

Answer and reasoning

WIP and cycle time can rise without more completed output

Additional incoming work accumulates unless another route or genuine bottleneck-capacity change handles it.

## Evidence and scope

Factory rates, costs, queues and ramp schedules are illustrative. Public capability pages do not provide a measured customer-level queue.

No current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.

## Sources

-   [TSMC — Intelligent Packaging Fab](https://www.tsmc.com/english/dedicatedFoundry/services/apm_intelligent_packaging_fab)
-   [Edwards — Semiconductor vacuum and abatement](https://www.edwardsvacuum.com/en-us/semiconductor)
-   [Advantest — Semiconductor test glossary](https://www.advantest.com/en/investors/ir-library/glossary/)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/fab-ramp-cycle-time-cfd2aa48bbf69749.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [MES, dispatch and process release](https://semiaifoundry.com/learn/atlas/manufacturing-execution-dispatch/)
-   [Wafer maps and good-die yield](https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/)

### Related lessons

-   [Cleanroom and subfab utilities](https://semiaifoundry.com/learn/atlas/cleanroom-subfab-utilities/)
-   [HBM silicon intensity and allocation](https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/)