{
  "schemaVersion": 1,
  "id": "atlas-lesson-fab-ramp-cycle-time",
  "title": "Cycle time, ramp and effective capacity",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Connects tool throughput, queues, qualification and yield learning over time.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/fab-ramp-cycle-time/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Fabrication / Control, test and ramp",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "Factory rates, costs, queues and ramp schedules are illustrative. Public capability pages do not provide a measured customer-level queue.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/fab-ramp-cycle-time-cfd2aa48bbf69749.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#fab-ramp-cycle-time",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "039f6a70e9f0c974b122466f67fdc5d5b30197af7ce85322fb550d76a6c599bf",
  "contentLength": 5091,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-fab-ramp-cycle-time.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-fab-ramp-cycle-time.md",
  "sections": [
    {
      "id": "section-1",
      "title": "Cycle time, ramp and effective capacity",
      "start": 53,
      "end": 427
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 427,
      "end": 1559
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1559,
      "end": 1587
    },
    {
      "id": "section-4",
      "title": "Little’s law",
      "start": 1587,
      "end": 2221
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 2221,
      "end": 2418
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2418,
      "end": 2824
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 2824,
      "end": 3083
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 3083,
      "end": 3284
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 3284,
      "end": 3313
    },
    {
      "id": "section-10",
      "title": "What happens if wafer starts rise while the final qualified bottleneck throughput stays fixed?",
      "start": 3313,
      "end": 3756
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 3756,
      "end": 4062
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 4062,
      "end": 4607
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 4607,
      "end": 4630
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 4630,
      "end": 4862
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 4862,
      "end": 5091
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#fab-ramp-cycle-time"
    },
    {
      "title": "TSMC — Intelligent Packaging Fab",
      "url": "https://www.tsmc.com/english/dedicatedFoundry/services/apm_intelligent_packaging_fab"
    },
    {
      "title": "Edwards — Semiconductor vacuum and abatement",
      "url": "https://www.edwardsvacuum.com/en-us/semiconductor"
    },
    {
      "title": "Advantest — Semiconductor test glossary",
      "url": "https://www.advantest.com/en/investors/ir-library/glossary/"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/fab-ramp-cycle-time-cfd2aa48bbf69749.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "MES, dispatch and process release",
      "url": "https://semiaifoundry.com/learn/atlas/manufacturing-execution-dispatch/"
    },
    {
      "title": "Wafer maps and good-die yield",
      "url": "https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/"
    },
    {
      "title": "Cleanroom and subfab utilities",
      "url": "https://semiaifoundry.com/learn/atlas/cleanroom-subfab-utilities/"
    },
    {
      "title": "HBM silicon intensity and allocation",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/"
    }
  ],
  "recordHash": "56ba930fe2b345fa2c0de25b05501a4a0b44bb7f8012c4884fb203ff4e5a7318",
  "contentFormat": "text/markdown",
  "content": "Fabrication / Control, test and ramp · Atlas v1.3.0\n\n# Cycle time, ramp and effective capacity\n\nConnects tool throughput, queues, qualification and yield learning over time.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#fab-ramp-cycle-time)Feature measurements, wafer maps and time-dependent production\n\nLearning objectiveInterpret time-dependent manufacturing capacity without confusing starts and released output.\n\n## The mechanism\n\nA factory’s output changes during ramp. Equipment is installed and qualified, process capability stabilizes, staffing and maintenance practices mature, and product yield evolves. Nameplate tool throughput describes only part of that path. Re-entrant processing and shared bottlenecks create waiting time between operations, while engineering holds and qualification gates can stop release. Wafer starts, work in process and good dies shipped are therefore different time-series quantities. The lesson follows a batch through a simple factory and asks which constraint determines completed output today, then separates announced future capacity from operating and product-qualified capacity.\n\n1.  Separate installed equipment from capacity qualified for the intended product route.\n2.  Convert repeated tool visits and shared product demand to a consistent load basis.\n3.  Track work-in-process, queues, holds and departures over time.\n4.  Combine throughput with measured release yield using nonoverlapping denominators.\n5.  Update the binding constraint as tools, yields or downstream assembly readiness change.\n\n## Science and assumptions\n\n### Little’s law\n\n$$\n\\mathrm{WIP}=X\\,T_{\\mathrm{cycle}}\n$$\n\nFor stable flow, average work in process equals throughput times mean cycle time.\n\nSymbols and units\n\nWIP\n\nAverage work-in-process inventory\n\ndeclared material units\n\nX\n\nStable throughput through the same boundary\n\nmaterial units/day\n\nT\\_cycle\n\nMean cycle time through that boundary\n\ndays\n\nWIP counts a consistent unit, throughput uses units/day and cycle time days, averaged over the same stable system.\n\nAssumptions Long-run stable flow with consistent boundaries. During ramp or a growing backlog, transient accounting is needed instead of naïve steady-state inference.\n\n## Engineering example\n\nSynthetic stable line: 500 wafers of WIP and 10 wafers/day throughput imply 50 days average cycle time. The equation does not prove a newly ramping line is already stable.\n\n## Distinctions and tradeoffs\n\nA capacity announcement or a tool’s rated wafers/hour is not equivalent to good dies shipped per month.\n\nRunning near full utilization can build queues and increase cycle time; spare capacity can absorb variation but costs money.\n\nThe synchronization of good logic dies, HBM, substrates and package capacity determines when accelerator demand can become delivered hardware.\n\n## Specifications and interfaces\n\nFlow metrics\n\nStarts, WIP, throughput and cycle time\n\nUse a common material boundary and calendar interval.\n\nCapacity state\n\nInstalled → qualified → producing → released\n\nEach transition requires evidence; dates can differ.\n\n### Interfaces\n\nQualified routes and resources Input\n\nTools, utilities, materials, labor and release criteria\n\nReleased output Output\n\nGood units available after their actual process and test history\n\n## Check your understanding\n\n### What happens if wafer starts rise while the final qualified bottleneck throughput stays fixed?\n\n1.  WIP and cycle time can rise without more completed output\n2.  Good output must rise in exact proportion\n3.  Every wafer instantly becomes a package\n\nAnswer and reasoning\n\nWIP and cycle time can rise without more completed output\n\nAdditional incoming work accumulates unless another route or genuine bottleneck-capacity change handles it.\n\n## Evidence and scope\n\nFactory rates, costs, queues and ramp schedules are illustrative. Public capability pages do not provide a measured customer-level queue.\n\nNo current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.\n\n## Sources\n\n-   [TSMC — Intelligent Packaging Fab](https://www.tsmc.com/english/dedicatedFoundry/services/apm_intelligent_packaging_fab)\n-   [Edwards — Semiconductor vacuum and abatement](https://www.edwardsvacuum.com/en-us/semiconductor)\n-   [Advantest — Semiconductor test glossary](https://www.advantest.com/en/investors/ir-library/glossary/)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/fab-ramp-cycle-time-cfd2aa48bbf69749.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [MES, dispatch and process release](https://semiaifoundry.com/learn/atlas/manufacturing-execution-dispatch/)\n-   [Wafer maps and good-die yield](https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/)\n\n### Related lessons\n\n-   [Cleanroom and subfab utilities](https://semiaifoundry.com/learn/atlas/cleanroom-subfab-utilities/)\n-   [HBM silicon intensity and allocation](https://semiaifoundry.com/learn/atlas/hbm-silicon-intensity/)"
}