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  "title": "Metrology, inspection and process windows",
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  "description": "Measures geometry and defects at the stage where a manufacturing decision can still be made.",
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  "revisionDate": "2026-10-07",
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  "topic": "Fabrication / Control, test and ramp",
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  "version": "1.3.0",
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      "title": "Metrology, inspection and process windows",
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      "title": "Which comparison best tests whether an apparent tool shift is a metrology artifact?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#fab-metrology-process-window"
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    {
      "title": "KLA — Chip Manufacturing 101",
      "url": "https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf"
    },
    {
      "title": "KLA — Practical Applications of Measurement System Analysis",
      "url": "https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf"
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      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "Lithography and pattern transfer",
      "url": "https://semiaifoundry.com/learn/atlas/lithography/"
    },
    {
      "title": "Chemical mechanical planarization",
      "url": "https://semiaifoundry.com/learn/atlas/cmp/"
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    {
      "title": "Coat, bake, expose and develop",
      "url": "https://semiaifoundry.com/learn/atlas/resist-track-development/"
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      "title": "Plasma and wet etch: selectivity and profile",
      "url": "https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/"
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      "title": "Wafer maps and good-die yield",
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  "content": "Fabrication / Control, test and ramp · Atlas v1.3.0\n\n# Metrology, inspection and process windows\n\nMeasures geometry and defects at the stage where a manufacturing decision can still be made.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#fab-metrology-process-window)Feature measurements, wafer maps and time-dependent production\n\nLearning objectiveInterpret stage-specific process windows while accounting for measurement uncertainty.\n\n## The mechanism\n\nInspection asks where suspected defects are; metrology measures quantities such as thickness, critical dimension, overlay or shape. Both depend on sampling and a measurement system with finite uncertainty. A process window is the region of conditions that meets several requirements together, potentially including transferred geometry and electrical behavior. It is not defined by one attractive wafer image or one average value. Wafer, field, pattern and tool variation can overlap. This lesson aligns measurements to their process stages and populations, then chooses a follow-up capable of distinguishing competing explanations before changing a production process.\n\n1.  Define each response at an explicit process state and physical feature.\n2.  Check calibration, repeatability and sampling before interpreting a shift as a process change.\n3.  Retain spatial and tool/lot structure rather than collapsing immediately to an average.\n4.  Evaluate the intersection of requirements across tested conditions.\n5.  Choose a discriminating follow-up and verify the downstream result before asserting a causal fix.\n\n## Science and assumptions\n\n### Observed variance model\n\n$$\n\\sigma_{\\mathrm{obs}}^2=\\sigma_{\\mathrm{process}}^2+\\sigma_{\\mathrm{measurement}}^2\n$$\n\nObserved variance is the sum of process variance and independent additive measurement-error variance.\n\nSymbols and units\n\nσ²\\_obs\n\nObserved response variance\n\nnm² for a dimension response\n\nσ²\\_process\n\nTrue process response variance\n\nsame squared response units\n\nσ²\\_measurement\n\nIndependent additive measurement-error variance\n\nsame squared response units\n\nVariances use squared units of the response, such as nm².\n\nAssumptions Independent additive random-error approximation. Systematic bias and correlated errors are not removed by subtracting variances.\n\n## Engineering example\n\nSynthetic measurement: 3 nm observed standard deviation and 2 nm independent metrology deviation imply √(9−4) ≈ 2.24 nm process deviation under the model. The calculation does not estimate an unknown measurement bias.\n\n## Distinctions and tradeoffs\n\nA tight distribution from a biased measurement system can still miss the actual product target.\n\nMore sensitive or denser measurement can reveal failures sooner but consumes time and may not sample every product-relevant feature.\n\nProcess control protects the large accumulated value of complex logic and memory flows and enables a stable yield ramp.\n\n## Specifications and interfaces\n\nPattern metrics\n\nCD, overlay, roughness and defectivity\n\nDifferent variables; retain units, stage and population.\n\nUncertainty\n\nRepeatability, bias and sampling\n\nA displayed number is not automatically the true feature value.\n\n### Interfaces\n\nWafer and equipment history Input\n\nMaterial state, sites, recipe and tool context\n\nControl evidence Output\n\nMeasurements, defects and uncertainty for a release decision\n\n## Check your understanding\n\n### Which comparison best tests whether an apparent tool shift is a metrology artifact?\n\n1.  Matched samples measured with a controlled repeatability/reference study\n2.  Different products measured at unrelated stages\n3.  A single wafer image with no calibration\n\nAnswer and reasoning\n\nMatched samples measured with a controlled repeatability/reference study\n\nA matched study can separate measurement variation from changes in the material population.\n\n## Evidence and scope\n\nSampling rates and acceptance windows are product-specific. Simulated maps illustrate patterns and do not diagnose a real fab excursion.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [KLA — Chip Manufacturing 101](https://www.kla.com/wp-content/uploads/ChipManufacturing101.pdf)\n-   [KLA — Practical Applications of Measurement System Analysis](https://www.kla.com/documents/5.3_Practical_Applications_of_MSA_Sutherland_KLA.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/fab-metrology-process-window-f655aad3076601f0.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)\n-   [Chemical mechanical planarization](https://semiaifoundry.com/learn/atlas/cmp/)\n\n### Related lessons\n\n-   [Coat, bake, expose and develop](https://semiaifoundry.com/learn/atlas/resist-track-development/)\n-   [Plasma and wet etch: selectivity and profile](https://semiaifoundry.com/learn/atlas/plasma-wet-etch-transfer/)\n-   [Wafer maps and good-die yield](https://semiaifoundry.com/learn/atlas/yield-wafer-defect-model/)"
}