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  "title": "EMIB and localized die-to-die bridges",
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  "description": "Places fine-routing silicon near adjacent die edges inside a substrate.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Packaging / Interposers, bridges and stacking",
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  "version": "1.3.0",
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      "title": "EMIB and localized die-to-die bridges",
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      "title": "Connection-yield sensitivity",
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      "title": "Which information is needed before claiming an EMIB-specific capacity bottleneck?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#emib-local-bridge"
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    {
      "title": "Intel Foundry — Accelerating HPC and AI",
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      "title": "Flip-chip assembly and organic substrates",
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      "title": "CoWoS-S and the silicon interposer route",
      "url": "https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/"
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      "title": "CoWoS-R and CoWoS-L: RDL and local silicon",
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  "content": "Packaging / Interposers, bridges and stacking · Atlas v1.3.0\n\n# EMIB and localized die-to-die bridges\n\nPlaces fine-routing silicon near adjacent die edges inside a substrate.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#emib-local-bridge)Multi-die package to selected joint; not dimensionally identical alternatives\n\nLearning objectiveExplain localized bridge geometry and preserve EMIB/EMIB-T boundaries.\n\n## The mechanism\n\nIntel’s EMIB uses embedded bridges to connect neighboring dies through a substrate-based assembly. Fine routing is concentrated at the relevant die-to-die boundaries instead of requiring one full-area silicon interposer. This changes where alignment, substrate construction and joint formation must succeed. A bridge is not an active processor merely because it is made of silicon. Public EMIB-T descriptions add through-silicon connections and power-delivery capabilities, so that variant must be labeled explicitly rather than silently drawn as original EMIB. Comparing bridge and interposer routes requires equivalent endpoints, power and test requirements, not a claim that eliminating one structure eliminates all package yield loss.\n\n1.  Identify adjacent dies and the edge interfaces that require dense interconnection.\n2.  Fabricate and embed the corresponding bridge structures into the compatible substrate route.\n3.  Align each die to both its local bridge interface and other substrate connections.\n4.  Complete joints and package structures, then verify electrical continuity and stress behavior.\n5.  Label EMIB-T-specific TSV/power features separately when comparing that disclosed variant.\n\n## Science and assumptions\n\n### Connection-yield sensitivity\n\n$$\nY_{\\mathrm{links}}\\approx(1-p)^N\n$$\n\nAll-link survival is approximately one minus per-link failure probability raised to the number of independent required connections.\n\nSymbols and units\n\nY\\_links\n\nProbability all required modeled connections survive\n\nfraction\n\np\n\nFailure probability of each independent connection\n\nfraction\n\nN\n\nNumber of required connections\n\ncount\n\nN is the number of required independent connections and p failure probability per connection.\n\nAssumptions Illustrative independence model for a defined population. Shared alignment and substrate failures create correlation; redundancy changes the result.\n\n## Engineering example\n\nSynthetic sensitivity: 10,000 independent required connections at p = 10⁻⁵ give about 90.5% all-good probability. That toy result explains sensitivity to many joints, not Intel’s measured assembly yield.\n\n## Distinctions and tradeoffs\n\nEliminating a full silicon interposer does not eliminate substrate, bridge-placement or final assembly losses.\n\nLocalized routing can avoid a full-area interposer but shifts demands to bridge embedding, substrate accuracy and die placement.\n\nBridge routes can connect compute chiplets and memory in large packages while preserving a different manufacturing dependency structure.\n\n## Specifications and interfaces\n\nBaseline EMIB\n\nLocalized embedded routing bridge\n\nA package interconnect structure near adjacent dies.\n\nEMIB-T distinction\n\nTSV-enabled extension in Intel’s disclosure\n\nRoadmap and offering status require a dated configuration.\n\n### Interfaces\n\nDies and bridge-bearing substrate Input\n\nCompatible edge interfaces and qualified substrate structures\n\nConnected multi-die package Output\n\nShort local die-to-die paths plus substrate power/I/O routing\n\n## Check your understanding\n\n### Which information is needed before claiming an EMIB-specific capacity bottleneck?\n\n1.  Any company-wide wafer capex number\n2.  A picture showing several bridges\n3.  Direct evidence scoped to that route and time period\n\nAnswer and reasoning\n\nDirect evidence scoped to that route and time period\n\nRoute architecture does not provide a measured manufacturing queue or allocation.\n\n## Evidence and scope\n\nThe Intel brief includes forecasts and manufacturer comparisons. No EMIB-specific queue, utilization or field failure rate is established.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/emib-local-bridge-c088c1cf60acdf36.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Flip-chip assembly and organic substrates](https://semiaifoundry.com/learn/atlas/flip-chip-abf-substrate/)\n-   [CoWoS-S and the silicon interposer route](https://semiaifoundry.com/learn/atlas/cowos-s-silicon-interposer/)\n\n### Related lessons\n\n-   [CoWoS-R and CoWoS-L: RDL and local silicon](https://semiaifoundry.com/learn/atlas/cowos-r-l-routing/)\n-   [Microbumps, reflow and thermocompression](https://semiaifoundry.com/learn/atlas/bump-thermocompression-assembly/)"
}