# DRAM die and memory banks Canonical: https://semiaifoundry.com/learn/atlas/dram-die/ Revision: 2026-10-07 Rights: https://semiaifoundry.com/ai-atlas/licenses.html Memory hierarchy · Atlas v1.3.0 # DRAM die and memory banks Stores dense arrays of charge-based bits and organizes them into banks for read, write, and refresh. [Explore in Atlas](https://semiaifoundry.com/ai-atlas/#dram-die)Nanometer-scale device features assembled into millimeter-scale banks and dies Learning objectiveFollow a bitline disturbance through sensing and restoration. ## The mechanism A DRAM die is mostly an organized landscape of memory cells. In the common one-transistor, one-capacitor cell, stored charge represents a bit and the transistor controls access to it. Word lines select rows; bit lines carry the small electrical changes that sense amplifiers detect and restore. The charge leaks, so refresh is part of normal operation. Banks provide opportunities for overlapping work, but timing constraints mean that an arbitrary stream of addresses does not behave like one continuous pipe. A memory bank organizes rows of cells; the stored bits collectively encode the weight and activation arrays that software reads and writes. 1. A selected word line enables access transistors, coupling the chosen memory cells to their bit lines. 2. Sense amplifiers detect and restore small charge-dependent signals so reads produce reliable digital values. 3. Refresh revisits stored rows before leakage destroys their contents, while banks schedule application accesses around maintenance. ## Science and assumptions ### A stored bit begins as a tiny voltage perturbation $$ \Delta V_{\mathrm{bitline}}=\frac{C_{\mathrm{cell}}}{C_{\mathrm{cell}}+C_{\mathrm{bitline}}}(V_{\mathrm{cell}}-V_{\mathrm{precharge}}) $$ Initial bit-line voltage change is the cell share of total capacitance times the initial cell-to-precharge voltage difference. Symbols and units ΔV\_bitline Initial bit-line voltage change V C\_cell Selected cell capacitance F C\_bitline Precharged bit-line capacitance F V\_cell Cell voltage before charge sharing V V\_precharge Bit-line precharge voltage V When the access transistor connects a selected cell to a precharged bit line, their capacitances share charge. Because the bit line can be much larger than the cell capacitance, the initial voltage change is small. A sense amplifier must detect its sign and restore a full logic level, connecting the microscopic capacitor directly to the digital bit used by software. Assumptions Ideal charge sharing before amplification, with fixed capacitances and no leakage, access resistance, coupling noise, or transistor threshold effects. Actual DRAM sensing and retention require a full circuit model. ## Engineering example A cell charge is shared with a bitline capacitance before the sense amplifier resolves and restores the value; parasitics reduce the ideal swing. ## Distinctions and tradeoffs DRAM retains information only while powered and refreshed. The trained model survives a power loss because a separate nonvolatile copy exists in storage. DRAM provides more bits per area than SRAM, but access and refresh require additional operations. Higher density must preserve enough electrical margin for reliable sensing. Billions of model parameters are ultimately stored as physical bit patterns. DRAM supplies the capacity that small on-chip SRAM structures cannot economically provide. ## Specifications and interfaces Cell model 1 transistor + 1 capacitor Common DRAM cell; schematic, not a manufacturer-specific process cross-section. State retention Volatile; periodic refresh Stored charge requires maintenance while powered. Example per-layer density 24 Gb = 3 GB Inferred average for 24 GB/8-layer and 36 GB/12-layer HBM3E examples. ### Interfaces Row/column selection Input Decoded memory commands Sensed data Output Restored digital values from selected cells Refresh control Input Operations that restore stored charge ## Check your understanding ### Why does conventional DRAM need refresh? 1. Stored capacitor charge gradually leaks away. 2. Every memory cell is an optical fiber. 3. Refresh downloads a new model from the network. Answer and reasoning Stored capacitor charge gradually leaks away. Charge-based storage is compact but not indefinitely stable. Periodic restoration keeps the bit values intact while power is available. ## Historical context ### 1968 · Dennard’s DRAM cell patent is granted Robert Dennard’s field-effect memory patent, filed in 1967 after his 1966 work at IBM, was granted on June 4, 1968. A compact access device and charge-storage element established the basis for dense dynamic memory, with periodic restoration as part of normal operation. [Robert Dennard: US3387286A, Field-effect transistor memory](https://patents.google.com/patent/US3387286A/en) ## Evidence and scope The expression is a simplified charge-sharing model. Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism. ## Sources - [Micron: How DRAM changed the world](https://www.micron.com/about/blog/memory/dram/how-dram-changed-the-world) - [Micron educator hub: Introduction to memory](https://www.micron.com/content/dam/micron/educatorhub/intro-to-memory/micron-intro-to-memory-presentation.pdf) - [Micron HBM3E](https://www.micron.com/products/memory/hbm/hbm3e) - [MIT Computation Structures: DRAM charge sharing](https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/f342551f652653e3ee0d0c56a926efeb_9eWKuWyXYKY.pdf) - [Robert Dennard: US3387286A, Field-effect transistor memory](https://patents.google.com/patent/US3387286A/en) [Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/dram-die-1a43a09c840bc357.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html) ## Continue exploring ### Foundations - [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/) - [Insulators and low-k films](https://semiaifoundry.com/learn/atlas/dielectric/) ### Related lessons - [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/) - [Through-silicon via](https://semiaifoundry.com/learn/atlas/through-silicon-via/) - [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/) - [Grace LPDDR5X memory](https://semiaifoundry.com/learn/atlas/lpddr-memory/)