# DRAM cells, arrays and peripheral circuits

Canonical: https://semiaifoundry.com/learn/atlas/dram-cell-array-fabrication/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

Memory / HBM fabrication and assembly · Atlas v1.3.0

# DRAM cells, arrays and peripheral circuits

Creates charge-storage cells and the circuitry needed to address, sense and restore them.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#dram-cell-array-fabrication)DRAM cell to vertical stack; routes and logical mapping are separate

Learning objectiveConnect DRAM fabrication geometry to storage, sensing and restoration.

## The mechanism

An HBM memory die contains DRAM arrays rather than a solid block of bits. A representative cell stores charge on a capacitor and uses an access transistor to connect it to a bitline. Wordlines select rows; sense amplifiers resolve a small voltage change and restore the data; peripheral circuits coordinate addressing and access. Manufacturing must create useful capacitance within a small footprint while controlling leakage, transistor behavior and array defects. Tall storage structures create deposition and etch challenges. This lesson connects the physical cell to a bank and keeps memory-cell fabrication separate from the later TSV, thinning and stack-assembly operations.

1.  Form access devices and the high-surface-area capacitor structures of the chosen cell route.
2.  Build wordlines and bitlines that connect many cells to selection and sensing circuitry.
3.  Activate a selected row so stored charge perturbs the precharged bitline.
4.  Sense the small signal and restore the cell state as part of the access cycle.
5.  Test retention, addressing and faults, then apply permitted repair before later integration.

## Science and assumptions

### Initial charge-sharing signal

$$
\Delta V_{\mathrm{bitline}}\approx\frac{C_{\mathrm{cell}}}{C_{\mathrm{cell}}+C_{\mathrm{bitline}}}(V_{\mathrm{cell}}-V_{\mathrm{precharge}})
$$

Initial bit-line perturbation is approximately the cell share of combined capacitance times the initial cell-to-precharge voltage difference.

Symbols and units

ΔV\_bitline

Initial sensed bit-line perturbation

V

C\_cell

Storage-cell capacitance

F

C\_bitline

Precharged bit-line capacitance

F

V\_cell

Initial cell voltage

V

V\_precharge

Initial bit-line precharge voltage

V

Capacitances use F and voltages V; the ratio is dimensionless.

Assumptions Ideal charge sharing before sense amplification, neglecting leakage, parasitics and access-transistor dynamics.

## Engineering example

Synthetic cell: $C_{\mathrm{cell}} = 20$ fF, $C_{\mathrm{bitline}} = 180$ fF and a 0.5 V initial difference give about 0.05 V bitline perturbation. A larger bitline capacitance reduces that initial signal.

## Distinctions and tradeoffs

Stacking more DRAM dies does not remove the need for refresh or make each cell directly accessible without array circuitry.

More capacitance can improve sensing and retention margin but becomes harder to manufacture in a smaller cell footprint.

Weights, activations and cache state in HBM ultimately depend on reliable charge storage and array access beneath the wide external interface.

## Specifications and interfaces

Cell roles

Storage capacitor and access transistor

A representative DRAM cell; actual process geometry is generation dependent.

Array roles

Wordline, bitline, sense amplifier and bank

Logical address groups are not the same objects as stacked die layers.

### Interfaces

Memory wafer process Input

Cell and peripheral-device integration plus repeated patterning

Testable DRAM die Output

Addressable arrays with retention, access and repair characteristics

## Check your understanding

### Why does a DRAM read need a sense amplifier?

1.  The cell contains a complete CPU
2.  A TSV reads every bit simultaneously
3.  Cell charge creates a small bitline change that must be resolved and restored

Answer and reasoning

Cell charge creates a small bitline change that must be resolved and restored

The cell capacitor is small relative to the bitline load, so charge sharing alone does not produce a robust full digital level.

## Evidence and scope

The geometry and capacitances are illustrative. No cell capacitor dimensions, refresh interval or proprietary HBM DRAM process is claimed.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Micron — Introduction to Memory](https://www.micron.com/content/dam/micron/educatorhub/intro-to-memory/micron-intro-to-memory-presentation.pdf)
-   [Synopsys — What Designers Need to Know About HBM3](https://www.synopsys.com/articles/hbm3-ip-dwtb.html)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/dram-cell-array-fabrication-574a79feed83c253.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [DRAM die and memory banks](https://semiaifoundry.com/learn/atlas/dram-die/)
-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)

### Related lessons

-   [ALD and self-limiting surface reactions](https://semiaifoundry.com/learn/atlas/ald-self-limiting-growth/)
-   [TSV formation, keep-out and backside reveal](https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/)
-   [HBM generations, channels, refresh and ECC](https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/)