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  "id": "atlas-lesson-dram-cell-array-fabrication",
  "title": "DRAM cells, arrays and peripheral circuits",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Creates charge-storage cells and the circuitry needed to address, sense and restore them.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/dram-cell-array-fabrication/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Memory / HBM fabrication and assembly",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "The geometry and capacitances are illustrative. No cell capacitor dimensions, refresh interval or proprietary HBM DRAM process is claimed.",
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  "sections": [
    {
      "id": "section-1",
      "title": "DRAM cells, arrays and peripheral circuits",
      "start": 54,
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      "id": "section-2",
      "title": "The mechanism",
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      "title": "Science and assumptions",
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      "id": "section-4",
      "title": "Initial charge-sharing signal",
      "start": 1611,
      "end": 2372
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      "title": "Engineering example",
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      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2603,
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      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 3025,
      "end": 3320
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      "id": "section-8",
      "title": "Interfaces",
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      "id": "section-9",
      "title": "Check your understanding",
      "start": 3525,
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    {
      "id": "section-10",
      "title": "Why does a DRAM read need a sense amplifier?",
      "start": 3554,
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      "title": "Evidence and scope",
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      "title": "Sources",
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      "id": "section-13",
      "title": "Continue exploring",
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      "id": "section-14",
      "title": "Foundations",
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      "end": 5031
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      "id": "section-15",
      "title": "Related lessons",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#dram-cell-array-fabrication"
    },
    {
      "title": "Micron — Introduction to Memory",
      "url": "https://www.micron.com/content/dam/micron/educatorhub/intro-to-memory/micron-intro-to-memory-presentation.pdf"
    },
    {
      "title": "Synopsys — What Designers Need to Know About HBM3",
      "url": "https://www.synopsys.com/articles/hbm3-ip-dwtb.html"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/dram-cell-array-fabrication-574a79feed83c253.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "DRAM die and memory banks",
      "url": "https://semiaifoundry.com/learn/atlas/dram-die/"
    },
    {
      "title": "Metal–oxide–semiconductor field-effect transistor",
      "url": "https://semiaifoundry.com/learn/atlas/mosfet/"
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    {
      "title": "ALD and self-limiting surface reactions",
      "url": "https://semiaifoundry.com/learn/atlas/ald-self-limiting-growth/"
    },
    {
      "title": "TSV formation, keep-out and backside reveal",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/"
    },
    {
      "title": "HBM generations, channels, refresh and ECC",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/"
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  "content": "Memory / HBM fabrication and assembly · Atlas v1.3.0\n\n# DRAM cells, arrays and peripheral circuits\n\nCreates charge-storage cells and the circuitry needed to address, sense and restore them.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#dram-cell-array-fabrication)DRAM cell to vertical stack; routes and logical mapping are separate\n\nLearning objectiveConnect DRAM fabrication geometry to storage, sensing and restoration.\n\n## The mechanism\n\nAn HBM memory die contains DRAM arrays rather than a solid block of bits. A representative cell stores charge on a capacitor and uses an access transistor to connect it to a bitline. Wordlines select rows; sense amplifiers resolve a small voltage change and restore the data; peripheral circuits coordinate addressing and access. Manufacturing must create useful capacitance within a small footprint while controlling leakage, transistor behavior and array defects. Tall storage structures create deposition and etch challenges. This lesson connects the physical cell to a bank and keeps memory-cell fabrication separate from the later TSV, thinning and stack-assembly operations.\n\n1.  Form access devices and the high-surface-area capacitor structures of the chosen cell route.\n2.  Build wordlines and bitlines that connect many cells to selection and sensing circuitry.\n3.  Activate a selected row so stored charge perturbs the precharged bitline.\n4.  Sense the small signal and restore the cell state as part of the access cycle.\n5.  Test retention, addressing and faults, then apply permitted repair before later integration.\n\n## Science and assumptions\n\n### Initial charge-sharing signal\n\n$$\n\\Delta V_{\\mathrm{bitline}}\\approx\\frac{C_{\\mathrm{cell}}}{C_{\\mathrm{cell}}+C_{\\mathrm{bitline}}}(V_{\\mathrm{cell}}-V_{\\mathrm{precharge}})\n$$\n\nInitial bit-line perturbation is approximately the cell share of combined capacitance times the initial cell-to-precharge voltage difference.\n\nSymbols and units\n\nΔV\\_bitline\n\nInitial sensed bit-line perturbation\n\nV\n\nC\\_cell\n\nStorage-cell capacitance\n\nF\n\nC\\_bitline\n\nPrecharged bit-line capacitance\n\nF\n\nV\\_cell\n\nInitial cell voltage\n\nV\n\nV\\_precharge\n\nInitial bit-line precharge voltage\n\nV\n\nCapacitances use F and voltages V; the ratio is dimensionless.\n\nAssumptions Ideal charge sharing before sense amplification, neglecting leakage, parasitics and access-transistor dynamics.\n\n## Engineering example\n\nSynthetic cell: $C_{\\mathrm{cell}} = 20$ fF, $C_{\\mathrm{bitline}} = 180$ fF and a 0.5 V initial difference give about 0.05 V bitline perturbation. A larger bitline capacitance reduces that initial signal.\n\n## Distinctions and tradeoffs\n\nStacking more DRAM dies does not remove the need for refresh or make each cell directly accessible without array circuitry.\n\nMore capacitance can improve sensing and retention margin but becomes harder to manufacture in a smaller cell footprint.\n\nWeights, activations and cache state in HBM ultimately depend on reliable charge storage and array access beneath the wide external interface.\n\n## Specifications and interfaces\n\nCell roles\n\nStorage capacitor and access transistor\n\nA representative DRAM cell; actual process geometry is generation dependent.\n\nArray roles\n\nWordline, bitline, sense amplifier and bank\n\nLogical address groups are not the same objects as stacked die layers.\n\n### Interfaces\n\nMemory wafer process Input\n\nCell and peripheral-device integration plus repeated patterning\n\nTestable DRAM die Output\n\nAddressable arrays with retention, access and repair characteristics\n\n## Check your understanding\n\n### Why does a DRAM read need a sense amplifier?\n\n1.  The cell contains a complete CPU\n2.  A TSV reads every bit simultaneously\n3.  Cell charge creates a small bitline change that must be resolved and restored\n\nAnswer and reasoning\n\nCell charge creates a small bitline change that must be resolved and restored\n\nThe cell capacitor is small relative to the bitline load, so charge sharing alone does not produce a robust full digital level.\n\n## Evidence and scope\n\nThe geometry and capacitances are illustrative. No cell capacitor dimensions, refresh interval or proprietary HBM DRAM process is claimed.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [Micron — Introduction to Memory](https://www.micron.com/content/dam/micron/educatorhub/intro-to-memory/micron-intro-to-memory-presentation.pdf)\n-   [Synopsys — What Designers Need to Know About HBM3](https://www.synopsys.com/articles/hbm3-ip-dwtb.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/dram-cell-array-fabrication-574a79feed83c253.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [DRAM die and memory banks](https://semiaifoundry.com/learn/atlas/dram-die/)\n-   [Metal–oxide–semiconductor field-effect transistor](https://semiaifoundry.com/learn/atlas/mosfet/)\n\n### Related lessons\n\n-   [ALD and self-limiting surface reactions](https://semiaifoundry.com/learn/atlas/ald-self-limiting-growth/)\n-   [TSV formation, keep-out and backside reveal](https://semiaifoundry.com/learn/atlas/hbm-tsv-reveal/)\n-   [HBM generations, channels, refresh and ECC](https://semiaifoundry.com/learn/atlas/hbm-channel-generation-ras/)"
}