{
  "schemaVersion": 1,
  "id": "atlas-lesson-ddr-memory",
  "title": "DDR5 server memory",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Provides expandable main memory for conventional host CPUs and their software working sets.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/ddr-memory/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Host platform",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "The formula uses the stated transfer-rate convention.",
  "contentCoverage": "published-lesson",
  "artifactUrl": "https://semiaifoundry.com/ai-atlas/lesson-data/ddr-memory-1e1336a29e90dcda.json",
  "interactiveUrl": "https://semiaifoundry.com/ai-atlas/#ddr-memory",
  "related": [],
  "supersedes": [],
  "supersededBy": [],
  "contentHash": "67ce9aa27f27d799ffff522d4ba14809965cd9ed84ca88b5187f1f095ae155c8",
  "contentLength": 5597,
  "jsonUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-ddr-memory.json",
  "markdownUrl": "https://semiaifoundry.com/agents/publications/atlas-lesson-ddr-memory.md",
  "sections": [
    {
      "id": "section-1",
      "title": "DDR5 server memory",
      "start": 30,
      "end": 358
    },
    {
      "id": "section-2",
      "title": "The mechanism",
      "start": 358,
      "end": 1535
    },
    {
      "id": "section-3",
      "title": "Science and assumptions",
      "start": 1535,
      "end": 1563
    },
    {
      "id": "section-4",
      "title": "Clock cycles and transfer rate are different units",
      "start": 1563,
      "end": 2867
    },
    {
      "id": "section-5",
      "title": "Engineering example",
      "start": 2867,
      "end": 2991
    },
    {
      "id": "section-6",
      "title": "Distinctions and tradeoffs",
      "start": 2991,
      "end": 3565
    },
    {
      "id": "section-7",
      "title": "Specifications and interfaces",
      "start": 3565,
      "end": 3932
    },
    {
      "id": "section-8",
      "title": "Interfaces",
      "start": 3932,
      "end": 4153
    },
    {
      "id": "section-9",
      "title": "Check your understanding",
      "start": 4153,
      "end": 4182
    },
    {
      "id": "section-10",
      "title": "At 4,800 MT/s and 64 data bits, what is the theoretical payload rate before workload effects?",
      "start": 4182,
      "end": 4492
    },
    {
      "id": "section-11",
      "title": "Evidence and scope",
      "start": 4492,
      "end": 4737
    },
    {
      "id": "section-12",
      "title": "Sources",
      "start": 4737,
      "end": 5220
    },
    {
      "id": "section-13",
      "title": "Continue exploring",
      "start": 5220,
      "end": 5243
    },
    {
      "id": "section-14",
      "title": "Foundations",
      "start": 5243,
      "end": 5406
    },
    {
      "id": "section-15",
      "title": "Related lessons",
      "start": 5406,
      "end": 5597
    }
  ],
  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#ddr-memory"
    },
    {
      "title": "Micron DDR5 DRAM",
      "url": "https://www.micron.com/products/memory/dram-components/ddr5-sdram"
    },
    {
      "title": "Micron DDR5 SDRAM: New Features",
      "url": "https://assets.micron.com/adobe/assets/urn%3Aaaid%3Aaem%3A5ea148c8-e3fe-489e-8489-99b1b9cdcd3c/renditions/original/as/ddr5-new-features-white-paper.pdf"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/ddr-memory-1e1336a29e90dcda.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "DRAM die and memory banks",
      "url": "https://semiaifoundry.com/learn/atlas/dram-die/"
    },
    {
      "title": "Host CPU",
      "url": "https://semiaifoundry.com/learn/atlas/host-cpu/"
    },
    {
      "title": "Compute baseboard and tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-baseboard/"
    },
    {
      "title": "Grace LPDDR5X memory",
      "url": "https://semiaifoundry.com/learn/atlas/lpddr-memory/"
    }
  ],
  "recordHash": "681fd1e87a116c26c1bdb6d387523064c12ef63da2285278566e94d15886fa9b",
  "contentFormat": "text/markdown",
  "content": "Host platform · Atlas v1.3.0\n\n# DDR5 server memory\n\nProvides expandable main memory for conventional host CPUs and their software working sets.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#ddr-memory)About 10-centimeter module class; multiple packaged DRAM devices\n\nLearning objectiveConvert a CAS latency and transfer rate into a time estimate.\n\n## The mechanism\n\nDDR memory modules connect to a CPU’s memory channels and hold the working state of programs while powered. They provide substantially more capacity than small processor caches and are commonly socketed for service or expansion. DDR5 divides a module’s data interface into independent subchannels and introduces reliability features within the DRAM. On-die error correction is not the same as end-to-end protection of the complete memory link. This atlas includes DDR5 as the conventional server branch: the Grace CPU in the GB200 reference system uses LPDDR5X instead. A DDR DIMM supplies the CPU memory path in that conventional server branch; its role and interface differ from a GPU’s nearby HBM. Bandwidth depends on channel count, transfer rate, ranks, and the supported population of the motherboard.\n\n1.  The CPU memory controller selects a channel and issues read or write commands to installed modules.\n2.  DRAM devices activate and access the relevant rows, transferring values across the module’s data subchannels.\n3.  Host software uses those values for its working set while refresh and error-management mechanisms preserve reliable operation.\n\n## Science and assumptions\n\n### Clock cycles and transfer rate are different units\n\n$$\nt_{\\mathrm{CAS}}=\\frac{2000\\,\\mathrm{CL}}{r_{\\mathrm{MT/s}}}\\,\\mathrm{ns}\n$$\n\nCAS timing in nanoseconds is 2000 times the CAS latency count divided by the numerical DDR transfer rate in megatransfers per second.\n\nInsert the rate number in MT/s, not transfers/s. This is CAS timing rather than complete CPU memory-access latency.\n\nSymbols and units\n\nt\\_CAS\n\nCAS column-read timing interval\n\nns\n\nCL\n\nCAS latency count\n\nmemory clock cycles\n\nr\\_MT/s\n\nNumerical effective DDR transfer rate expressed in MT/s\n\nMT/s numerical value\n\n2000\n\nConversion factor for two transfers per clock and MT/s to ns\n\nconversion factor\n\nCL is CAS latency measured in memory clock cycles. Double-data-rate signaling performs two transfers per clock, so a transfer rate of r million transfers per second corresponds to half that clock frequency. The formula converts a timing count into nanoseconds, showing why a larger CL number at a faster transfer rate can still represent similar absolute latency.\n\nAssumptions CAS timing conversion for DDR with two transfers per clock. It covers the column-read timing interval, not total CPU load latency, row activation, precharge, queues, refresh, or burst completion. Use the selected device’s supported CL and rate together.\n\n## Engineering example\n\nFor CL=40 at 6400 MT/s, the first-order CAS estimate is 12.5 ns; controller scheduling adds delay.\n\n## Distinctions and tradeoffs\n\nDDR5 on-die ECC protects internal DRAM operations; it is not a substitute for all end-to-end server memory error protection. Grace also uses LPDDR5X rather than these socketed DDR DIMMs.\n\nSocketed memory offers capacity and service flexibility, but wide board routes consume energy and constrain speed. Adding modules can change the supported operating rate and access behavior.\n\nDatasets, preprocessing buffers, retrieval indexes, and service state often live in host memory. Adequate capacity prevents expensive movement to slower storage.\n\n## Specifications and interfaces\n\nDDR5 data organization\n\nTwo 32-bit subchannels per DIMM\n\nData bits only; server ECC modules carry additional check bits.\n\nExample transfer rate\n\n4,800 MT/s\n\nDDR5 example, not a universal current maximum.\n\nExample payload peak\n\n38.4 GB/s per 64-bit module\n\nCalculated as 4,800 million transfers/s × 8 bytes; before workload effects.\n\n### Interfaces\n\nCPU memory commands Input\n\nAddressed reads, writes, and maintenance\n\nHost data Output\n\nApplication and operating-system memory values\n\nRefresh and power Input\n\nRetention maintenance and electrical supply\n\n## Check your understanding\n\n### At 4,800 MT/s and 64 data bits, what is the theoretical payload rate before workload effects?\n\n1.  38.4 GB/s.\n2.  4,800 GB/s.\n3.  38.4 TB/s.\n\nAnswer and reasoning\n\n38.4 GB/s.\n\nEach transfer carries 8 data bytes. Multiplying 4.8 billion transfers per second by 8 bytes gives 38.4 billion bytes per second.\n\n## Evidence and scope\n\nThe formula uses the stated transfer-rate convention.\n\nPlace read-only weights and mutable KV across specified tiers and inspect transfer paths; no HBF shipping-system benchmark or universal memory semantics are implied.\n\n## Sources\n\n-   [Micron DDR5 DRAM](https://www.micron.com/products/memory/dram-components/ddr5-sdram)\n-   [Micron DDR5 SDRAM: New Features](https://assets.micron.com/adobe/assets/urn%3Aaaid%3Aaem%3A5ea148c8-e3fe-489e-8489-99b1b9cdcd3c/renditions/original/as/ddr5-new-features-white-paper.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/ddr-memory-1e1336a29e90dcda.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [DRAM die and memory banks](https://semiaifoundry.com/learn/atlas/dram-die/)\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n\n### Related lessons\n\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)\n-   [Grace LPDDR5X memory](https://semiaifoundry.com/learn/atlas/lpddr-memory/)"
}