# From architecture contract to a chip

Canonical: https://semiaifoundry.com/learn/atlas/crg-chip-design-realization/
Revision: 2026-10-07
Rights: https://semiaifoundry.com/ai-atlas/licenses.html

· Atlas v1.3.0

# From architecture contract to a chip

Traverses specification, RTL, verification, synthesis, physical design, tapeout and wafer test.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#crg-chip-design-realization)RTL → layout → masks → wafer test

Learning objectiveName the design transformations and closure gates between an architecture contract and a tested die.

## The mechanism

A chip design is a sequence of constrained transformations. The architecture contract becomes microarchitecture and RTL, then a verified netlist, a placed-and-routed layout, mask data and a process-specific tapeout. The PDK supplies rules and models; timing, power, signal integrity, design-for-test and manufacturability gates prevent an attractive logical design from becoming an untestable or unbuildable die. The CRG makes communication explicit at every handoff: module interfaces, clock and power domains, floorplan distances, package bumps and external links all carry obligations that must survive the transformation.

1.  Refine the architecture contract into clocked state, interfaces and microarchitectural resources.
2.  Verify behavior and synthesize the design using process-specific libraries and models.
3.  Place, route and close timing, power, signal integrity, DFT and physical rules.
4.  Generate masks and send a reviewed tapeout to the chosen foundry process.
5.  Probe, bin and feed measured results back into the design and architecture loop.

## Science and assumptions

### Timing closure boundary

$$
T_{\mathrm{clock}}\ge t_{CQ}+t_{\mathrm{logic}}+t_{\mathrm{setup}}+t_{\mathrm{uncertainty}}
$$

The clock period must cover clock-to-Q, logic, setup and uncertainty terms for the specified timing path.

Symbols and units

T\_clock

Available clock period

s

t\_CQ

Launch register clock-to-Q delay for the selected analysis

s

t\_logic

Combinational path delay

s

t\_setup

Capture setup-time requirement

s

t\_uncertainty

Declared timing uncertainty budget

s

The clock period must cover launch delay, combinational logic, setup time and an uncertainty budget at the declared path boundary.

Assumptions A simplified single-clock path; skew, variation, multi-cycle paths and asynchronous crossings need explicit treatment.

## Engineering example

A 1 GHz target gives a 1 ns period. If clock-to-Q, logic, setup and uncertainty sum to 1.08 ns, the design fails the declared boundary even if its functional simulation is correct.

## Distinctions and tradeoffs

Tapeout is not physical realization; wafer yield, test coverage, packaging and system qualification remain.

More margin and redundancy can improve yield or reliability while consuming area, power, schedule and mask complexity.

The models and kernels that drive AI systems become useful only when their numerical and communication assumptions are realized in a qualified chip and package.

## Specifications and interfaces

Design chain

Spec → microarchitecture → RTL → netlist → layout → tapeout

A representative flow; organizations partition responsibilities differently.

Closure gates

Functional, timing, power, DFT, physical and manufacturability

Passing one gate does not imply the others pass.

### Interfaces

Architecture contract Input

Behavior, interfaces, budgets and verification targets

Tapeout package Output

Mask data, signoff evidence and test structures

## Check your understanding

### Why does a PDK matter in chip design?

1.  It replaces functional verification
2.  It connects design rules and models to a particular manufacturing process
3.  It guarantees every die will pass final test

Answer and reasoning

It connects design rules and models to a particular manufacturing process

A PDK ties the design abstractions to process constraints, but yield and qualification still require measurement.

## Evidence and scope

The sequence is a representative educational flow. Foundry-specific PDK content and proprietary signoff data are not disclosed.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [Semi AI Foundry — Communication Theory of Computation Realization](https://semiaifoundry.com/updates/communication-theory-of-computation-realization/)
-   [imec — CMOS scaling and system co-optimization](https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/crg-chip-design-realization-1a06711ce64cbdb4.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Architecture is a contract between computation and silicon](https://semiaifoundry.com/learn/atlas/crg-architecture-contract/)
-   [Standard-cell library and physical design](https://semiaifoundry.com/learn/atlas/standard-cell/)
-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)

### Related lessons

-   [Metrology, inspection and process windows](https://semiaifoundry.com/learn/atlas/fab-metrology-process-window/)
-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)