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  "title": "CoWoS-S and the silicon interposer route",
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  "description": "Integrates logic and memory over a shared silicon routing structure.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Packaging / Interposers, bridges and stacking",
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  "license": null,
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  "version": "1.3.0",
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      "title": "CoWoS-S and the silicon interposer route",
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      "title": "The mechanism",
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      "title": "Convergent assembly ceiling",
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      "title": "Engineering example",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "If logic dies are plentiful but compatible HBM stacks are scarce, what constrains package output?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#cowos-s-silicon-interposer"
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    {
      "title": "TSMC — CoWoS",
      "url": "https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm"
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      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Flip-chip assembly and organic substrates",
      "url": "https://semiaifoundry.com/learn/atlas/flip-chip-abf-substrate/"
    },
    {
      "title": "DFT, probe, binning and known-good die",
      "url": "https://semiaifoundry.com/learn/atlas/known-good-die-test/"
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      "title": "Interposer and redistribution layers",
      "url": "https://semiaifoundry.com/learn/atlas/interposer/"
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    {
      "title": "High-bandwidth memory stack",
      "url": "https://semiaifoundry.com/learn/atlas/hbm-stack/"
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      "title": "CoWoS-R and CoWoS-L: RDL and local silicon",
      "url": "https://semiaifoundry.com/learn/atlas/cowos-r-l-routing/"
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    {
      "title": "HBM stack assembly, repair and staged test",
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  "content": "Packaging / Interposers, bridges and stacking · Atlas v1.3.0\n\n# CoWoS-S and the silicon interposer route\n\nIntegrates logic and memory over a shared silicon routing structure.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#cowos-s-silicon-interposer)Multi-die package to selected joint; not dimensionally identical alternatives\n\nLearning objectiveTrace separate logic, memory and interposer paths into a CoWoS-S package.\n\n## The mechanism\n\nCoWoS-S is a TSMC integration route built around a silicon interposer. Logic dies and separately manufactured HBM stacks meet on that fine-routing structure, which then connects to a package substrate. The interposer is a fabricated component with wiring and vertical connections; it is not the same object as the accelerator die or the organic substrate. Its area, routing, test status and assembly requirements enter the package plan. The process graph therefore converges several supply paths instead of showing HBM emerging from the logic wafer. The cross-section preserves each input’s identity through joining and final package test.\n\n1.  Fabricate and inspect the silicon interposer and its routing/vertical connection structures.\n2.  Manufacture and screen logic dies and memory stacks on their separate upstream routes.\n3.  Align and join components to compatible interposer locations using the selected assembly process.\n4.  Connect the integrated assembly to the package substrate and complete mechanical/thermal structures.\n5.  Test the final package and retain die, memory and interposer genealogy for failures.\n\n## Science and assumptions\n\n### Convergent assembly ceiling\n\n$$\nN_{\\mathrm{packages}}\\le\\min\\!\\left(\\frac{N_{\\mathrm{logic}}}{l},\\frac{N_{\\mathrm{HBM}}}{h},N_{\\mathrm{interposer}},N_{\\mathrm{substrate}},C_{\\mathrm{assembly}}\\right)\n$$\n\nSupported packages are bounded by the smallest compatible input stream after logic and HBM counts are converted to packages, and by assembly capacity over the same interval.\n\nSymbols and units\n\nN\\_packages\n\nPackages supportable during the selected interval\n\npackages\n\nN\\_logic\n\nAvailable good compatible logic dies\n\ndies\n\nl\n\nLogic dies required per package\n\ndies/package\n\nN\\_HBM\n\nAvailable good compatible memory stacks\n\nstacks\n\nh\n\nHBM stacks required per package\n\nstacks/package\n\nN\\_interposer\n\nOne-interposer-per-package compatible input count\n\npackage-equivalent inputs\n\nN\\_substrate\n\nOne-substrate-per-package compatible input count\n\npackage-equivalent inputs\n\nC\\_assembly\n\nAssembly starts possible during the same interval\n\npackages\n\nN terms count available good compatible inputs; l and h are logic dies and HBM stacks required per package; $C_{\\mathrm{assembly}}$ uses packages over the same interval.\n\nAssumptions A resource ceiling before new assembly losses, qualification, scheduling and inventory constraints; it is not a yield forecast.\n\n## Engineering example\n\nSynthetic week: 100 logic dies, 320 good HBM stacks and four stacks/package permit at most 80 packages before other constraints, even if 100 interposers and substrates are ready.\n\n## Distinctions and tradeoffs\n\nHBM is not made after the logic die as a continuation of the same wafer process; its manufacturing path converges at integration.\n\nA shared dense routing plane supports many connections but requires interposer fabrication and high-value multi-component assembly.\n\nThe interposer enables many short parallel connections between compute and HBM; package supply still depends on every converging input.\n\n## Specifications and interfaces\n\nRouting structure\n\nSilicon interposer\n\nDistinct from active logic, HBM stacks and organic substrate.\n\nAssembly inputs\n\nGood logic + good memory + interposer + substrate\n\nCounts require compatible product configurations and timing.\n\n### Interfaces\n\nScreened components Input\n\nLogic, HBM, interposer and substrate with compatible interfaces\n\nIntegrated package Output\n\nFine die-to-memory routing and a board-facing package interface\n\n## Check your understanding\n\n### If logic dies are plentiful but compatible HBM stacks are scarce, what constrains package output?\n\n1.  The required HBM stack supply can become the binding input\n2.  Only the logic wafer-start rate\n3.  The silicon atom count of the substrate\n\nAnswer and reasoning\n\nThe required HBM stack supply can become the binding input\n\nEach finished package consumes a complete compatible set of components.\n\n## Evidence and scope\n\nTSMC’s public page establishes route identity. Exact process order, materials and customer allocation are not fully public.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [TSMC — CoWoS](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/cowos-s-silicon-interposer-1d403bb1f11e02c6.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Flip-chip assembly and organic substrates](https://semiaifoundry.com/learn/atlas/flip-chip-abf-substrate/)\n-   [DFT, probe, binning and known-good die](https://semiaifoundry.com/learn/atlas/known-good-die-test/)\n\n### Related lessons\n\n-   [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/)\n-   [High-bandwidth memory stack](https://semiaifoundry.com/learn/atlas/hbm-stack/)\n-   [CoWoS-R and CoWoS-L: RDL and local silicon](https://semiaifoundry.com/learn/atlas/cowos-r-l-routing/)\n-   [HBM stack assembly, repair and staged test](https://semiaifoundry.com/learn/atlas/hbm-stack-assembly-test/)"
}