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  "id": "atlas-lesson-compute-tray",
  "title": "GB200 compute tray",
  "category": "learning",
  "format": "Atlas lesson",
  "description": "Packages CPU–GPU compute and local support hardware into a serviceable rack unit.",
  "canonicalUrl": "https://semiaifoundry.com/learn/atlas/compute-tray/",
  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Rack integration",
  "series": null,
  "license": null,
  "rightsUrl": "https://semiaifoundry.com/ai-atlas/licenses.html",
  "version": "1.3.0",
  "status": "Published educational lesson",
  "evidenceScope": "These counts apply to the documented one-rack GB200 NVL72 configuration already cited in the lesson. They do not describe every rack product or predict installed, available or productive capacity.",
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  "sections": [
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      "id": "section-1",
      "title": "GB200 compute tray",
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      "id": "section-2",
      "title": "The mechanism",
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      "title": "Science and assumptions",
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      "title": "Reference-system composition",
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      "title": "Specifications and interfaces",
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      "title": "Interfaces",
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      "title": "Check your understanding",
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      "title": "How many Blackwell GPUs are in the illustrated GB200 compute tray?",
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      "title": "Evidence and scope",
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      "title": "Sources",
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      "title": "Continue exploring",
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      "title": "Foundations",
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      "id": "section-15",
      "title": "Related lessons",
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  "citations": [
    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#compute-tray"
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    {
      "title": "NVIDIA — DGX GB200 SuperPOD Components",
      "url": "https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html"
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    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
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    {
      "title": "Compute baseboard and tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-baseboard/"
    },
    {
      "title": "Integrated accelerator rack: GB200 NVL72 example",
      "url": "https://semiaifoundry.com/learn/atlas/rack/"
    },
    {
      "title": "NVLink switch tray and scale-up fabric",
      "url": "https://semiaifoundry.com/learn/atlas/nvlink-switch/"
    },
    {
      "title": "NVLink copper cable cartridge",
      "url": "https://semiaifoundry.com/learn/atlas/cable-cartridge/"
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    {
      "title": "Coolant distribution unit and separated loops",
      "url": "https://semiaifoundry.com/learn/atlas/cdu/"
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    {
      "title": "Rack power shelf and DC busbar",
      "url": "https://semiaifoundry.com/learn/atlas/power-shelf/"
    },
    {
      "title": "CUDA programming and runtime layer",
      "url": "https://semiaifoundry.com/learn/atlas/cuda/"
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  "content": "Rack integration · Atlas v1.3.0\n\n# GB200 compute tray\n\nPackages CPU–GPU compute and local support hardware into a serviceable rack unit.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#compute-tray)1U rack module; components enlarged in cutaway\n\nLearning objectiveTranslate a named rack’s tray configuration into component counts without treating packaging levels as interchangeable.\n\n## The mechanism\n\nThe compute tray is a physical execution unit within the rack. In the documented GB200 NVL72 example, each one-unit tray contains two Grace CPUs and four Blackwell GPUs, organized as two Grace Blackwell Superchips. Local support includes networking, storage, management, and cold plates. Short CPU–GPU links serve a different role from the NVLink switch network that joins GPUs across trays. The atlas slides out one tray and expands its boards so viewers can follow those boundaries without mistaking a CPU–GPU module for the entire rack. The tray also connects to shared power and cooling systems. Its compute hardware remains dependent on these external services even when shown as an isolated assembly.\n\n1.  Connect CPU and GPU resources within each Superchip.\n2.  Join two Superchips and support interfaces in the tray.\n3.  Attach the tray to rack-wide communication, power, and coolant infrastructure.\n\n## Science and assumptions\n\n### Reference-system composition\n\n$$\n\\begin{aligned}18\\,\\mathrm{trays}\\times4\\,\\mathrm{GPUs/tray}&=72\\,\\mathrm{GPUs}\\\\18\\,\\mathrm{trays}\\times2\\,\\mathrm{CPUs/tray}&=36\\,\\mathrm{CPUs}\\end{aligned}\n$$\n\nIn the stated reference, 18 trays with four GPUs each contain 72 GPUs. The same 18 trays with two CPUs each contain 36 CPUs.\n\nSymbols and units\n\n18 trays\n\nCompute-tray count in the named GB200 NVL72 reference\n\ntrays\n\n4 GPUs/tray\n\nGPU count per reference compute tray\n\nGPUs/tray\n\n2 CPUs/tray\n\nCPU count per reference compute tray\n\nCPUs/tray\n\nCounting at explicit assembly boundaries prevents confusion between a GPU, a Superchip, a tray, and a rack. The same boundaries define service and communication domains.\n\nAssumptions Documented one-rack GB200 NVL72 example only; other products and configurations differ.\n\n## Engineering example\n\nFor the cited GB200 NVL72 reference, 18 compute trays × 4 GPUs per tray = 72 GPUs, while 18 × 2 CPUs per tray = 36 CPUs. The 18 trays are not 18 GPUs, and the GPU count is not a count of all underlying logic dies.\n\n## Distinctions and tradeoffs\n\nTwo GB200 Superchips contain four GPUs and two CPUs; a Superchip is not a synonym for a single GPU.\n\nModular trays aid integration and service. Dense local packaging leaves constrained space for connections and cooling.\n\nA tray contains the arithmetic and memory working on model partitions. Its local interfaces shape how those partitions obtain data.\n\n## Specifications and interfaces\n\nGB200 tray example\n\n4 GPUs + 2 Grace CPUs\n\nTwo GB200 Superchips in one compute tray.\n\nRack height\n\n1U\n\nDocumented DGX GB200 compute-tray form factor.\n\nCPU–GPU link\n\nNVLink-C2C\n\nLocal coherent interface; distinct from rack NVLink switching.\n\n### Interfaces\n\nRack services Input\n\nElectrical power, coolant, network traffic, and commands\n\nAccelerated work Output\n\nComputed tensors and communication with peer trays\n\n## Check your understanding\n\n### How many Blackwell GPUs are in the illustrated GB200 compute tray?\n\n1.  One\n2.  Four\n3.  Seventy-two\n\nAnswer and reasoning\n\nFour\n\nThe documented tray contains two Superchips, each combining two Blackwell GPUs and one Grace CPU.\n\n## Evidence and scope\n\nThese counts apply to the documented one-rack GB200 NVL72 configuration already cited in the lesson. They do not describe every rack product or predict installed, available or productive capacity.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [NVIDIA — DGX GB200 SuperPOD Components](https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/compute-tray-b65ff15b5c9539eb.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Compute baseboard and tray](https://semiaifoundry.com/learn/atlas/compute-baseboard/)\n\n### Related lessons\n\n-   [Integrated accelerator rack: GB200 NVL72 example](https://semiaifoundry.com/learn/atlas/rack/)\n-   [NVLink switch tray and scale-up fabric](https://semiaifoundry.com/learn/atlas/nvlink-switch/)\n-   [NVLink copper cable cartridge](https://semiaifoundry.com/learn/atlas/cable-cartridge/)\n-   [Coolant distribution unit and separated loops](https://semiaifoundry.com/learn/atlas/cdu/)\n-   [Rack power shelf and DC busbar](https://semiaifoundry.com/learn/atlas/power-shelf/)\n-   [CUDA programming and runtime layer](https://semiaifoundry.com/learn/atlas/cuda/)"
}