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  "id": "atlas-lesson-compute-baseboard",
  "title": "Compute baseboard and tray",
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  "description": "Integrates processors, memory, adapters, power, cooling, and service interfaces into an operational node.",
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  "revisionDate": "2026-10-07",
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  "topic": "System integration",
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      "title": "Compute baseboard and tray",
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      "title": "The mechanism",
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      "title": "Science and assumptions",
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      "title": "Impedance discontinuities reflect fast signals",
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      "title": "Specifications and interfaces",
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      "title": "Check your understanding",
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      "title": "Why inspect a compute tray’s topology before distributing a workload?",
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      "title": "Continue exploring",
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      "title": "Foundations",
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      "title": "Related lessons",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#compute-baseboard"
    },
    {
      "title": "NVIDIA DGX GB200 SuperPOD reference components",
      "url": "https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html"
    },
    {
      "title": "NVIDIA GB200 NVL multi-node tuning: system topology",
      "url": "https://docs.nvidia.com/multi-node-nvlink-systems/multi-node-tuning-guide/system.html"
    },
    {
      "title": "Texas Instruments: High-Speed Layout Guidelines",
      "url": "https://www.ti.com/lit/pdf/SCAA082A"
    },
    {
      "title": "Published lesson data",
      "url": "https://semiaifoundry.com/ai-atlas/lesson-data/compute-baseboard-3218c9a079eac9cd.json"
    },
    {
      "title": "Atlas releases and licensing",
      "url": "https://semiaifoundry.com/ai-atlas/licenses.html"
    },
    {
      "title": "GPU logic dies",
      "url": "https://semiaifoundry.com/learn/atlas/gpu-die/"
    },
    {
      "title": "Package substrate",
      "url": "https://semiaifoundry.com/learn/atlas/package-substrate/"
    },
    {
      "title": "PCI Express interconnect",
      "url": "https://semiaifoundry.com/learn/atlas/pcie-interface/"
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    {
      "title": "Host CPU",
      "url": "https://semiaifoundry.com/learn/atlas/host-cpu/"
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    {
      "title": "Grace Blackwell Superchip",
      "url": "https://semiaifoundry.com/learn/atlas/grace-blackwell-superchip/"
    },
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      "url": "https://semiaifoundry.com/learn/atlas/network-adapter/"
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    {
      "title": "NVMe solid-state storage",
      "url": "https://semiaifoundry.com/learn/atlas/nvme-storage/"
    },
    {
      "title": "Voltage regulator module",
      "url": "https://semiaifoundry.com/learn/atlas/voltage-regulator/"
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    {
      "title": "Liquid-cooling coldplate",
      "url": "https://semiaifoundry.com/learn/atlas/coldplate/"
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    {
      "title": "Baseboard management controller",
      "url": "https://semiaifoundry.com/learn/atlas/management-controller/"
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    {
      "title": "GB200 compute tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-tray/"
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  "content": "System integration · Atlas v1.3.0\n\n# Compute baseboard and tray\n\nIntegrates processors, memory, adapters, power, cooling, and service interfaces into an operational node.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#compute-baseboard)Roughly rack-width board/tray assembly; published 1 RU height\n\nLearning objectiveUse an impedance discontinuity to explain why a logically connected board trace can distort a signal.\n\n## The mechanism\n\nThe baseboard is where separate components become a coordinated machine. Its traces and connectors join processors, memory, storage, network adapters, management, and power circuits. A compute tray adds mechanical support, cooling connections, and interfaces that let the assembly slide into a rack. Topology matters: which GPU reaches which NIC, which devices share a PCIe path, and where CPU memory sits can all affect performance. Board signal routes, power distribution and cooling connections impose different constraints on the same operating assembly. This view is a logical reconstruction based on published block diagrams, not a manufacturing drawing. The serviceable tray is the bridge between package-scale engineering and rack-scale operations.\n\n1.  The board physically mounts the computing, memory, I/O, control, and power components and connects their electrical interfaces.\n2.  The tray integrates that board with structural support, cooling paths, and rack-facing connectors.\n3.  Power, data, management, and heat flow through separate but coordinated paths while the node executes its workload.\n\n## Science and assumptions\n\n### Impedance discontinuities reflect fast signals\n\n$$\n\\Gamma=\\frac{Z_{\\mathrm{load}}-Z_0}{Z_{\\mathrm{load}}+Z_0}\n$$\n\nThe voltage reflection coefficient is load impedance minus characteristic impedance divided by their sum.\n\nSymbols and units\n\nΓ\n\nVoltage reflection coefficient\n\ndimensionless (potentially complex)\n\nZ\\_load\n\nTermination impedance\n\nΩ\n\nZ₀\n\nTransmission-line characteristic impedance\n\nΩ\n\nZ0 is the transmission-line characteristic impedance and Zload is the termination impedance. Γ is the voltage reflection coefficient: a matched resistive load gives zero reflection, an open approaches +1, and a short approaches −1. Traces, vias, connectors, and package transitions must be designed together because reflected energy can distort the eye opening used to distinguish high-speed bits.\n\nAssumptions An ideal linear transmission line at a single termination, with real resistances for the simple limiting examples. Loss, frequency-dependent impedance, differential coupling, equalization, and multiple discontinuities require fuller channel analysis.\n\n## Engineering example\n\nSynthetic resistive termination: a 50 Ω line meeting a 75 Ω load has reflection coefficient Γ = (75 − 50)/(75 + 50) = 0.2. A 1 V incident wave therefore has a 0.2 V reflected wave at that boundary. A matched 50 Ω load gives Γ = 0.\n\n## Distinctions and tradeoffs\n\nA compute tray is not just a row of GPUs. CPU affinity, network paths, power delivery, cooling, and service connections all affect its practical behavior.\n\nDense integration shortens paths and saves space but complicates routing, cooling, and repair. A good board design balances peak performance with manufacturability and serviceability.\n\nThe GPU’s performance is useful only when data, power, and heat can move through the surrounding node. The tray makes those dependencies physically explicit.\n\n## Specifications and interfaces\n\nDGX GB200 tray\n\n2 Grace CPUs + 4 Blackwell GPUs\n\nPublished compute-tray configuration.\n\nMechanical height\n\n1 RU per compute tray\n\nDGX GB200 reference; 1 RU is 44.45 mm nominal rack-unit spacing.\n\nTray count in NVL72\n\n18 compute trays\n\nFour GPUs per tray gives 72 GPUs in the rack.\n\n### Interfaces\n\nPower and coolant Input\n\nRack distribution to board regulators and coldplates\n\nExternal network Output\n\nScale-out and management connections\n\nGPU fabric Output\n\nNVLink connections toward rack switching\n\n## Check your understanding\n\n### Why inspect a compute tray’s topology before distributing a workload?\n\n1.  Every component has an identical path to every other component.\n2.  Topology only changes the tray’s appearance.\n3.  Shared links and device proximity can change communication costs.\n\nAnswer and reasoning\n\nShared links and device proximity can change communication costs.\n\nTopology reveals which paths are local, shared, or remote. Work placement can avoid unnecessary traffic and contention.\n\n## Evidence and scope\n\nThis is the lesson’s single-termination linear transmission-line model. Values are synthetic; differential geometry, frequency response, loss, multiple reflections and receiver behavior need a complete channel model.\n\nNo current calculator directly models this lesson’s main mechanism. Use the library for related bounds while retaining their stated omissions.\n\n## Sources\n\n-   [NVIDIA DGX GB200 SuperPOD reference components](https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html)\n-   [NVIDIA GB200 NVL multi-node tuning: system topology](https://docs.nvidia.com/multi-node-nvlink-systems/multi-node-tuning-guide/system.html)\n-   [Texas Instruments: High-Speed Layout Guidelines](https://www.ti.com/lit/pdf/SCAA082A)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/compute-baseboard-3218c9a079eac9cd.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [GPU logic dies](https://semiaifoundry.com/learn/atlas/gpu-die/)\n-   [Package substrate](https://semiaifoundry.com/learn/atlas/package-substrate/)\n-   [PCI Express interconnect](https://semiaifoundry.com/learn/atlas/pcie-interface/)\n\n### Related lessons\n\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n-   [Grace Blackwell Superchip](https://semiaifoundry.com/learn/atlas/grace-blackwell-superchip/)\n-   [Network interface adapter](https://semiaifoundry.com/learn/atlas/network-adapter/)\n-   [NVMe solid-state storage](https://semiaifoundry.com/learn/atlas/nvme-storage/)\n-   [Voltage regulator module](https://semiaifoundry.com/learn/atlas/voltage-regulator/)\n-   [Liquid-cooling coldplate](https://semiaifoundry.com/learn/atlas/coldplate/)\n-   [Baseboard management controller](https://semiaifoundry.com/learn/atlas/management-controller/)\n-   [GB200 compute tray](https://semiaifoundry.com/learn/atlas/compute-tray/)"
}