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  "title": "Cache coherence and NUMA placement",
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  "description": "Keeps shared cache lines consistent while preserving awareness of physical memory location.",
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  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Processing architectures",
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      "title": "Cache coherence and NUMA placement",
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      "title": "Two cores update different counters in the same cache line. Why might they interfere?",
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      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#coherence-numa"
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      "title": "What is NUMA? Linux kernel 6.6 documentation",
      "url": "https://www.kernel.org/doc/html/v6.6/mm/numa.html"
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      "title": "Host CPU",
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      "title": "Shared L2 cache",
      "url": "https://semiaifoundry.com/learn/atlas/l2-cache/"
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      "title": "Out-of-order CPU pipeline",
      "url": "https://semiaifoundry.com/learn/atlas/cpu-out-of-order/"
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      "url": "https://semiaifoundry.com/learn/atlas/ddr-memory/"
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  "content": "Processing architectures · Atlas v1.3.0\n\n# Cache coherence and NUMA placement\n\nKeeps shared cache lines consistent while preserving awareness of physical memory location.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#coherence-numa)Core to multi-socket server; diagrams are logical\n\nLearning objectiveSeparate consistency, synchronization and physical locality in shared-memory systems.\n\n## The mechanism\n\nMultiple CPU cores can cache copies of the same memory line. A coherence protocol tracks copies and coordinates ownership when a core writes. Coherence provides an agreement about values; it does not make every access equally close or eliminate software synchronization. In a NUMA system, memory controllers belong to different locality domains, so an address may be directly attached to one CPU and reached over a link from another. Thread placement and allocation policy determine which path dominates. The Linux kernel documents this distinction and exposes memory policy controls for local, bound and interleaved allocation.\n\n1.  Map an address to its physical NUMA node and identify where the requesting thread is running.\n2.  Look for a valid local cache copy before issuing a request toward a memory controller or another cache.\n3.  On a write, obtain the protocol’s required ownership and invalidate or update conflicting cached copies.\n4.  Place frequently used pages near their workers, or deliberately spread pages when aggregate bandwidth matters more.\n5.  Measure remote accesses and cache-line transfers; change allocation and worker affinity together when diagnosing a bottleneck.\n\n## Science and assumptions\n\n### Average access path\n\n$$\nL_{\\mathrm{avg}}=pL_{\\mathrm{local}}+(1-p)L_{\\mathrm{remote}}\n$$\n\nMean latency is the local-access fraction times local latency plus the remaining fraction times remote latency.\n\nSymbols and units\n\nL\\_avg\n\nMean access latency in the two-path model\n\nns\n\np\n\nLocal-path access fraction\n\nfraction\n\nL\\_local\n\nLocal-path latency\n\nns\n\nL\\_remote\n\nRemote-path latency\n\nns\n\np is the fraction of accesses using the local path; L values are latency in ns. The average is a first diagnostic, not a tail-latency estimate.\n\nAssumptions Two paths and independent requests; excludes cache hits, overlap and queueing.\n\n## Engineering example\n\nSynthetic two-path example: 75% of requests at 80 ns and 25% at 160 ns gives a 100 ns average. Moving pages changes the fractions; simply adding cores does not shorten either path.\n\n## Distinctions and tradeoffs\n\nCache coherence is neither a guarantee of low latency nor a substitute for locks, atomics or a language memory model.\n\nInterleaving pages can balance memory bandwidth, while placing pages locally can reduce latency; the best choice depends on access sharing and thread migration.\n\nInput pipelines and CPU-managed inference caches can stall accelerators when pages repeatedly cross sockets or writable metadata bounces between cores.\n\n## Specifications and interfaces\n\nCoherence granularity\n\nCache line\n\nIndependent variables can still share one coherence unit.\n\nNUMA latency\n\nLocal and remote paths\n\nNanoseconds depend on machine topology and contention; no universal ratio.\n\n### Interfaces\n\nCore load/store Input\n\nAddress, ownership request and ordering requirements\n\nInter-socket fabric Output\n\nRemote data or coherence ownership messages\n\n## Check your understanding\n\n### Two cores update different counters in the same cache line. Why might they interfere?\n\n1.  The line’s ownership may move between cores\n2.  Different variables can never interfere\n3.  NUMA forces all writes to disk\n\nAnswer and reasoning\n\nThe line’s ownership may move between cores\n\nFalse sharing occurs because ownership is managed at cache-line granularity even though the variables are logically independent.\n\n## Evidence and scope\n\nTopology illustrations omit protocol state details. Local-versus-remote numbers are invented for calculation, not measurements of a named CPU.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [What is NUMA? Linux kernel 6.6 documentation](https://www.kernel.org/doc/html/v6.6/mm/numa.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/coherence-numa-e5a3b6b81d4eff19.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Host CPU](https://semiaifoundry.com/learn/atlas/host-cpu/)\n-   [Shared L2 cache](https://semiaifoundry.com/learn/atlas/l2-cache/)\n\n### Related lessons\n\n-   [Out-of-order CPU pipeline](https://semiaifoundry.com/learn/atlas/cpu-out-of-order/)\n-   [DDR5 server memory](https://semiaifoundry.com/learn/atlas/ddr-memory/)\n-   [Full memory hierarchy and input path](https://semiaifoundry.com/learn/atlas/memory-hierarchy-route/)"
}