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  "revisionDate": "2026-10-07",
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      "title": "Chemical mechanical planarization",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#cmp"
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    {
      "title": "Applied Materials — Chemical Mechanical Planarization",
      "url": "https://www.appliedmaterials.com/us/en/semiconductor/products/shape/cmp.html"
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      "title": "MIT — Control of Wafer-Scale Nonuniformity in CMP",
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      "title": "Wafer and fabrication hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/silicon-wafer/"
    },
    {
      "title": "Copper conductor and barrier",
      "url": "https://semiaifoundry.com/learn/atlas/copper-conductor/"
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    {
      "title": "Lithography and pattern transfer",
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  "content": "Fabrication · Atlas v1.3.0\n\n# Chemical mechanical planarization\n\nRestores controlled surface planarity between fabrication stages.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#cmp)Wafer-scale operation controlling nanometer-scale films\n\nLearning objectiveExplain why planarization needs both removal and local uniformity.\n\n## The mechanism\n\nBuilding one patterned layer leaves topography that can interfere with the next. Chemical mechanical planarization combines chemical action with a moving pad and abrasive-containing slurry to remove excess material and control surface height. It can expose embedded features and establish a workable foundation for later processing. The process is not simply polishing the finished chip until it shines: material selectivity, remaining film thickness, and uniformity across the wafer matter. The atlas shows a partially planarized wiring surface and the desired plane, making visible why layer stacking requires repeated surface preparation. Measurement and endpoint control keep removal from erasing the structures that the preceding stages worked to create.\n\n1.  Identify excess material and topography left by previous fabrication stages.\n2.  Use coupled chemical and mechanical action to remove material toward a controlled plane.\n3.  Measure the remaining surface and stop before critical underlying structures are damaged.\n\n## Science and assumptions\n\n### Preston removal relation\n\n$$\n\\mathrm{RR}\\approx k_P P v_{\\mathrm{rel}}\n$$\n\nRemoval rate is approximately the calibrated Preston coefficient times pressure times relative speed.\n\nSymbols and units\n\nRR\n\nMaterial removal rate\n\nm/s\n\nk\\_P\n\nCalibrated Preston coefficient for these units\n\nPa⁻¹\n\nP\n\nContact pressure in the model\n\nPa\n\nv\\_rel\n\nRelative sliding speed\n\nm/s\n\nRemoval rate RR is modeled using pressure P, relative sliding speed $v_{\\mathrm{rel}}$, and an empirical coefficient $k_{P}$. Chemistry, pad condition, and local pattern geometry influence the coefficient and local behavior.\n\nAssumptions Empirical approximation over a calibrated regime, not a universal material law or manufacturing recipe; no process settings are prescribed.\n\n## Engineering example\n\nA nominally cleared film can still leave slow sites or overpolish fast sites; the CMP lab exposes the two-sided envelope.\n\n## Distinctions and tradeoffs\n\nCMP is not merely cosmetic polishing after chip completion; it supports integration between selected fabrication stages.\n\nPlanarity supports the next layer. Excess removal or uneven polishing can damage existing features.\n\nLayered chips require controlled surfaces to remain buildable. CMP helps turn repeated fabrication steps into connected, reliable structures.\n\n## Specifications and interfaces\n\nCombined mechanism\n\nChemical + mechanical\n\nA coupled material-removal process.\n\nControlled outputs\n\nPlanarity and thickness\n\nBoth local patterns and wafer-scale uniformity matter.\n\nIntegration role\n\nRepeated fabrication step\n\nUsed at selected device and wiring stages.\n\n### Interfaces\n\nUneven patterned surface Input\n\nExcess film and topography\n\nPlanarized surface Output\n\nFoundation for subsequent layers\n\n## Check your understanding\n\n### Why is surface planarity important?\n\n1.  It makes the final chip reflective enough to compute\n2.  It eliminates the need for lithography\n3.  It prepares a controlled foundation for later layers\n\nAnswer and reasoning\n\nIt prepares a controlled foundation for later layers\n\nSubsequent patterning and material integration depend on controlled surface height and remaining thickness.\n\n## Evidence and scope\n\nThe nominal residual is not a spatial mean and is not a bonding-readiness guarantee.\n\nCompare nominal and local removal-rate extremes at a shared polish time; dishing, erosion and bond readiness are not predicted.\n\n## Sources\n\n-   [Applied Materials — Chemical Mechanical Planarization](https://www.appliedmaterials.com/us/en/semiconductor/products/shape/cmp.html)\n-   [MIT — Control of Wafer-Scale Nonuniformity in CMP](https://dspace.mit.edu/server/api/core/bitstreams/3190d1a1-d6a9-40d3-83ed-85939659b1f0/content)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/cmp-765ad3af18f3b8ed.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Wafer and fabrication hierarchy](https://semiaifoundry.com/learn/atlas/silicon-wafer/)\n-   [Copper conductor and barrier](https://semiaifoundry.com/learn/atlas/copper-conductor/)\n\n### Related lessons\n\n-   [Lithography and pattern transfer](https://semiaifoundry.com/learn/atlas/lithography/)\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n-   [Interposer and redistribution layers](https://semiaifoundry.com/learn/atlas/interposer/)"
}