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  "title": "NVLink copper cable cartridge",
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  "description": "Provides dense physical signal connections between compute and switch trays.",
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  "publishedDate": null,
  "revisionDate": "2026-10-07",
  "author": null,
  "topic": "Rack integration",
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  "version": "1.3.0",
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      "title": "NVLink copper cable cartridge",
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      "title": "The mechanism",
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      "title": "Why does the atlas sample the cable paths?",
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    {
      "title": "Explore in Atlas",
      "url": "https://semiaifoundry.com/ai-atlas/#cable-cartridge"
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    {
      "title": "NVIDIA — Blackwell Rack-Scale Interconnection",
      "url": "https://blogs.nvidia.com/blog/blackwell-ai-inference/"
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    {
      "title": "NVIDIA — DGX GB Rack Scale Systems Hardware Guide",
      "url": "https://docs.nvidia.com/dgx/dgxgb200-user-guide/hardware.html"
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    {
      "title": "NVIDIA — DGX GB200 SuperPOD Components",
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      "title": "NVLink GPU interface",
      "url": "https://semiaifoundry.com/learn/atlas/nvlink-port/"
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      "title": "On-chip metal and via hierarchy",
      "url": "https://semiaifoundry.com/learn/atlas/interconnect/"
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      "title": "Integrated accelerator rack: GB200 NVL72 example",
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      "title": "GB200 compute tray",
      "url": "https://semiaifoundry.com/learn/atlas/compute-tray/"
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      "url": "https://semiaifoundry.com/learn/atlas/nvlink-switch/"
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  "content": "Rack integration · Atlas v1.3.0\n\n# NVLink copper cable cartridge\n\nProvides dense physical signal connections between compute and switch trays.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#cable-cartridge)Meter-scale cable assembly containing many short links\n\nLearning objectiveSeparate propagation delay from serialization time on a physical link.\n\n## The mechanism\n\nA rack-wide fabric needs a physical transmission path as well as switch chips. The GB200 system uses a passive copper cable-cartridge backplane with blind-mate tray connections. That arrangement concentrates many short high-speed paths in a managed assembly rather than requiring every tray connection to be manually routed as an exposed cable. The atlas reveals the cartridge as a dense set of point-to-point paths and distinguishes it from the logical network drawn on top. Copper is not inherently obsolete: appropriate short-distance links can be effective, while optical links serve other reaches and system requirements. Connector integrity, signal quality, topology, and service access all affect whether theoretical bandwidth becomes reliable communication.\n\n1.  Map GPU endpoint connections to the required switch connections.\n2.  Bundle the physical copper paths into the cartridge structure.\n3.  Mate trays to the backplane so the logical fabric has a continuous signal path.\n\n## Science and assumptions\n\n### Propagation and serialization\n\n$$\nt_{\\mathrm{link}}\\gtrsim\\frac{L}{v_{\\mathrm{prop}}}+\\frac{S}{B_{\\mathrm{payload}}}\n$$\n\nLink time is approximately bounded below by propagation distance divided by propagation speed, plus payload bytes divided by payload bandwidth.\n\nSymbols and units\n\nt\\_link\n\nOne-hop link time in the simplified model\n\ns\n\nL\n\nPath length\n\nm\n\nv\\_prop\n\nSignal propagation speed along the medium\n\nm/s\n\nS\n\nPayload size\n\nbytes\n\nB\\_payload\n\nPayload serialization bandwidth\n\nbytes/s\n\nA link has propagation time along its length and serialization time to place the payload onto the channel. Short distance does not remove serialization or protocol overhead.\n\nAssumptions Simple one-hop link model; buffering, coding, connector loss, retransmission, and routing can add further cost.\n\n## Engineering example\n\nSynthetic one-hop link: 2 m at an assumed propagation speed of 2 × 10⁸ m/s adds 10 ns. Serializing a 1 kB payload at 25 GB/s adds 40 ns. Their sum is 50 ns before coding, connectors, buffering or retransmission.\n\n## Distinctions and tradeoffs\n\nA drawn connection is not merely abstract: a working rack needs its physical conductor, connectors, and signal margins.\n\nShort copper paths can serve dense racks well. Signal integrity and connector complexity constrain physical design.\n\nDense model communication requires real conductors and connectors. Cabling makes the rack fabric physically realizable.\n\n## Specifications and interfaces\n\nGB200 link medium\n\nPassive copper\n\nRack-scale NVLink cable-cartridge backplane.\n\nTray connection\n\nBlind-mate connectors\n\nDocumented rear-side connection scheme.\n\nPublished scale\n\nOver 5,000 copper cables\n\nNVIDIA rack description; illustration samples paths for legibility.\n\n### Interfaces\n\nCompute-tray connectors Input\n\nHigh-speed electrical signals\n\nSwitch-tray connectors Output\n\nMapped physical NVLink paths\n\n## Check your understanding\n\n### Why does the atlas sample the cable paths?\n\n1.  Thousands of physical paths would obscure the topology at viewing scale\n2.  The rack has only one real cable\n3.  Each visible cable represents a neural-network layer\n\nAnswer and reasoning\n\nThousands of physical paths would obscure the topology at viewing scale\n\nThe reference rack contains thousands of cables. A sampled rendering preserves the structural lesson without pretending to show every conductor.\n\n## Evidence and scope\n\nLength, speed and payload rate are teaching assumptions rather than specifications for a cable cartridge. A physical cable route is distinct from the logical collective or network topology that uses it.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [NVIDIA — Blackwell Rack-Scale Interconnection](https://blogs.nvidia.com/blog/blackwell-ai-inference/)\n-   [NVIDIA — DGX GB Rack Scale Systems Hardware Guide](https://docs.nvidia.com/dgx/dgxgb200-user-guide/hardware.html)\n-   [NVIDIA — DGX GB200 SuperPOD Components](https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/cable-cartridge-f4c862ca63ac4f0e.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [NVLink GPU interface](https://semiaifoundry.com/learn/atlas/nvlink-port/)\n-   [On-chip metal and via hierarchy](https://semiaifoundry.com/learn/atlas/interconnect/)\n\n### Related lessons\n\n-   [Integrated accelerator rack: GB200 NVL72 example](https://semiaifoundry.com/learn/atlas/rack/)\n-   [GB200 compute tray](https://semiaifoundry.com/learn/atlas/compute-tray/)\n-   [NVLink switch tray and scale-up fabric](https://semiaifoundry.com/learn/atlas/nvlink-switch/)\n-   [Optical transceiver and fiber link](https://semiaifoundry.com/learn/atlas/optics/)"
}