# Backside power and design–technology co-optimization

Canonical: https://semiaifoundry.com/learn/atlas/backside-power-dtco/
Revision: 2026-10-07
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Fabrication / BEOL and co-design · Atlas v1.3.0

# Backside power and design–technology co-optimization

Changes physical power routing and evaluates the device, layout and system consequences together.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#backside-power-dtco)Contacts to multilayer wires and backside; geometric scale varies

Learning objectiveEvaluate backside power as a coupled design and manufacturing decision.

## The mechanism

Power wires and signal wires compete for space and electrical margin. Backside power delivery moves parts of the power network to the opposite side of the wafer through a route that requires additional integration, thinning and connection structures. It can relieve frontside routing constraints, but power still must reach devices reliably and heat still must leave the package. Design–technology co-optimization evaluates cell layout, device structures and routing together; system–technology co-optimization extends that reasoning to partitioning and memory placement. The right comparison asks whether the complete manufacturable system improves at fixed workload requirements, not whether one isolated transistor or wiring metric improves.

1.  Start with the current and routing demands of a defined architecture and workload.
2.  Compare frontside and backside power paths using compatible device and cell assumptions.
3.  Include the thinning, backside connection and alignment operations required by each route.
4.  Analyze DC drop, transient supply noise, signal timing and thermal consequences together.
5.  Recheck yield, test access and package compatibility before claiming a system improvement.

## Science and assumptions

### Supply-path budget

$$
\Delta V\approx IR+L\frac{\mathrm dI}{\mathrm dt}
$$

First-order supply excursion is approximately resistive drop plus inductance times current slew rate.

Symbols and units

ΔV

Voltage excursion under the declared current/path sign convention

V

I

Path current

A

R

Lumped path resistance

Ω

L

Lumped path inductance

H

t

Time

s

dI/dt

Current slew rate

A/s

Voltage drop ΔV in V, current I in A, resistance R in Ω, inductance L in H and slew dI/dt in A/s.

Assumptions First-order lumped path model; distributed power networks and decoupling require frequency-dependent analysis.

## Engineering example

Synthetic DC example: a 20 A current through 2 mΩ loses 40 mV before transient effects. Halving that resistance recovers 20 mV, but additional routing or process costs still belong in the comparison.

## Distinctions and tradeoffs

Backside power does not make supply resistance zero or remove the package’s thermal problem.

Relieving frontside congestion can add backside process complexity, alignment demands and new thermal or test considerations.

AI arrays can create substantial current transients and routing demand; integration choices influence sustained operation as well as nominal density.

## Specifications and interfaces

Design boundary

Device → cell → die → package

Benefits and costs can appear at different levels.

Power metric

Voltage drop and delivery impedance

DC and transient behavior require distinct analyses.

### Interfaces

Workload and physical design Input

Current demand, signal routes and technology options

Integrated power architecture Output

Device connections, manufacturing route and system constraints

## Check your understanding

### What makes a backside-power comparison meaningful?

1.  Only comparing a routing illustration
2.  Assuming every backside process has perfect yield
3.  A common workload and complete device/layout/package assumptions

Answer and reasoning

A common workload and complete device/layout/package assumptions

Benefits in one physical layer can be offset or amplified elsewhere; a consistent system boundary is necessary.

## Evidence and scope

Intel’s brief includes announced roadmap capabilities. The lesson explains mechanisms and does not equate those announcements with a universal qualified flow.

Use the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.

## Sources

-   [imec — CMOS scaling](https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling)
-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/backside-power-dtco-5a6a59fdd09da2a1.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Wire resistance, low-k dielectrics and reliability](https://semiaifoundry.com/learn/atlas/interconnect-rc-materials/)

### Related lessons

-   [Voltage regulator module](https://semiaifoundry.com/learn/atlas/voltage-regulator/)
-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)
-   [GPU logic dies](https://semiaifoundry.com/learn/atlas/gpu-die/)