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  "title": "Backside power and design–technology co-optimization",
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  "description": "Changes physical power routing and evaluates the device, layout and system consequences together.",
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      "title": "Backside power and design–technology co-optimization",
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      "url": "https://semiaifoundry.com/ai-atlas/#backside-power-dtco"
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      "title": "imec — CMOS scaling",
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      "title": "Intel Foundry — Accelerating HPC and AI",
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      "title": "Wire resistance, low-k dielectrics and reliability",
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      "title": "Voltage regulator module",
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  "content": "Fabrication / BEOL and co-design · Atlas v1.3.0\n\n# Backside power and design–technology co-optimization\n\nChanges physical power routing and evaluates the device, layout and system consequences together.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#backside-power-dtco)Contacts to multilayer wires and backside; geometric scale varies\n\nLearning objectiveEvaluate backside power as a coupled design and manufacturing decision.\n\n## The mechanism\n\nPower wires and signal wires compete for space and electrical margin. Backside power delivery moves parts of the power network to the opposite side of the wafer through a route that requires additional integration, thinning and connection structures. It can relieve frontside routing constraints, but power still must reach devices reliably and heat still must leave the package. Design–technology co-optimization evaluates cell layout, device structures and routing together; system–technology co-optimization extends that reasoning to partitioning and memory placement. The right comparison asks whether the complete manufacturable system improves at fixed workload requirements, not whether one isolated transistor or wiring metric improves.\n\n1.  Start with the current and routing demands of a defined architecture and workload.\n2.  Compare frontside and backside power paths using compatible device and cell assumptions.\n3.  Include the thinning, backside connection and alignment operations required by each route.\n4.  Analyze DC drop, transient supply noise, signal timing and thermal consequences together.\n5.  Recheck yield, test access and package compatibility before claiming a system improvement.\n\n## Science and assumptions\n\n### Supply-path budget\n\n$$\n\\Delta V\\approx IR+L\\frac{\\mathrm dI}{\\mathrm dt}\n$$\n\nFirst-order supply excursion is approximately resistive drop plus inductance times current slew rate.\n\nSymbols and units\n\nΔV\n\nVoltage excursion under the declared current/path sign convention\n\nV\n\nI\n\nPath current\n\nA\n\nR\n\nLumped path resistance\n\nΩ\n\nL\n\nLumped path inductance\n\nH\n\nt\n\nTime\n\ns\n\ndI/dt\n\nCurrent slew rate\n\nA/s\n\nVoltage drop ΔV in V, current I in A, resistance R in Ω, inductance L in H and slew dI/dt in A/s.\n\nAssumptions First-order lumped path model; distributed power networks and decoupling require frequency-dependent analysis.\n\n## Engineering example\n\nSynthetic DC example: a 20 A current through 2 mΩ loses 40 mV before transient effects. Halving that resistance recovers 20 mV, but additional routing or process costs still belong in the comparison.\n\n## Distinctions and tradeoffs\n\nBackside power does not make supply resistance zero or remove the package’s thermal problem.\n\nRelieving frontside congestion can add backside process complexity, alignment demands and new thermal or test considerations.\n\nAI arrays can create substantial current transients and routing demand; integration choices influence sustained operation as well as nominal density.\n\n## Specifications and interfaces\n\nDesign boundary\n\nDevice → cell → die → package\n\nBenefits and costs can appear at different levels.\n\nPower metric\n\nVoltage drop and delivery impedance\n\nDC and transient behavior require distinct analyses.\n\n### Interfaces\n\nWorkload and physical design Input\n\nCurrent demand, signal routes and technology options\n\nIntegrated power architecture Output\n\nDevice connections, manufacturing route and system constraints\n\n## Check your understanding\n\n### What makes a backside-power comparison meaningful?\n\n1.  Only comparing a routing illustration\n2.  Assuming every backside process has perfect yield\n3.  A common workload and complete device/layout/package assumptions\n\nAnswer and reasoning\n\nA common workload and complete device/layout/package assumptions\n\nBenefits in one physical layer can be offset or amplified elsewhere; a consistent system boundary is necessary.\n\n## Evidence and scope\n\nIntel’s brief includes announced roadmap capabilities. The lesson explains mechanisms and does not equate those announcements with a universal qualified flow.\n\nUse the manufacturing investigation to trace compatible inputs, assembly and operating constraints; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [imec — CMOS scaling](https://www.imec-int.com/en/expertise/cmos-advanced/compute/cmos-scaling)\n-   [Intel Foundry — Accelerating HPC and AI](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/backside-power-dtco-5a6a59fdd09da2a1.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Wire resistance, low-k dielectrics and reliability](https://semiaifoundry.com/learn/atlas/interconnect-rc-materials/)\n\n### Related lessons\n\n-   [Voltage regulator module](https://semiaifoundry.com/learn/atlas/voltage-regulator/)\n-   [Temporary bonding, thinning and singulation](https://semiaifoundry.com/learn/atlas/temporary-carrier-thinning/)\n-   [GPU logic dies](https://semiaifoundry.com/learn/atlas/gpu-die/)"
}