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      "title": "Analog and photonic arithmetic research",
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    {
      "title": "An energy-efficient analog chip for AI inference",
      "url": "https://research.ibm.com/blog/analog-ai-chip-inference"
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      "title": "Parallel convolutional processing using an integrated photonic tensor core",
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  "content": "Processing architectures · Atlas v1.3.0\n\n# Analog and photonic arithmetic research\n\nExplores physical multiply accumulation with explicit conversion and accuracy limits.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#analog-photonic-research)Network endpoint to wafer; electrical and optical views are conceptual\n\nLearning objectiveDistinguish a physical arithmetic demonstration from a complete production accelerator claim.\n\n## The mechanism\n\nIn analog in-memory computing, stored conductance can encode a weight and an applied voltage can encode an input. Currents combine to form a multiply–accumulate result that must be sensed and often digitized. IBM has demonstrated mixed-signal phase-change-memory research chips using this principle. Photonic tensor-core research instead encodes and combines signals using optical components, with electronic interfaces still required around the computation. Both approaches can reduce certain data movements or exploit physical parallelism, but noise, drift, calibration, conversion and unsupported operations determine complete-system usefulness. Research demonstrations establish a mechanism and measured experiment, not automatic production readiness for large AI services.\n\n1.  Choose how numerical values are represented by conductance, voltage or an optical signal.\n2.  Program weights and calibrate the physical response, including device variation and drift.\n3.  Perform the physical combination that approximates the desired matrix operation.\n4.  Sense and convert the result, accounting for noise and the precision required by the next stage.\n5.  Evaluate model quality and total energy including peripherals, communication and operations performed outside the analog or optical core.\n\n## Science and assumptions\n\n### Ideal conductance accumulation\n\n$$\nI_j=\\sum_i G_{ij}V_i\n$$\n\nIn the ideal conductance-array model, each output current sums input voltage times its corresponding conductance.\n\nThis electrical conductance equation models an analog crossbar mechanism; it is not a universal equation for every photonic architecture.\n\nSymbols and units\n\nIⱼ\n\nOutput current at column j\n\nA\n\nGᵢⱼ\n\nProgrammed conductance from input i to output j\n\nS (siemens)\n\nVᵢ\n\nApplied input voltage\n\nV\n\ni,j\n\nInput and output indices\n\ninteger indices\n\nGij is conductance in siemens, Vi voltage in volts and Ij current in amperes; the sum represents an ideal linear dot product.\n\nAssumptions Linear devices, negligible wire drops and ideal readout; real arrays require calibration and may use differential encoding.\n\n## Engineering example\n\nSynthetic error budget: if sensing and weight drift each consume part of a permissible error margin, a larger array may need recalibration or wider digital correction even when its core operation is fast.\n\n## Distinctions and tradeoffs\n\nLight does not make data movement or heat disappear, and an analog multiply–accumulate does not supply arbitrary exact digital arithmetic.\n\nPhysical parallelism may reduce core arithmetic energy, while precision restoration, calibration and data conversion can consume much of the apparent benefit.\n\nInference tolerance to numerical error creates opportunities, but model quality and full operator coverage must survive real device variations.\n\n## Specifications and interfaces\n\nEvidence status\n\nResearch demonstration\n\nLaboratory arithmetic is separate from a qualified deployed service.\n\nAccounting boundary\n\nArray plus converters, control and memory\n\nLaser or conversion energy must be counted where the architecture requires it.\n\n### Interfaces\n\nEncoded inputs and weights Input\n\nVoltages/conductances or optical signals\n\nReadout and digital control Output\n\nDigitized results, calibration feedback and subsequent operations\n\n## Check your understanding\n\n### What belongs in a fair analog-versus-digital energy comparison?\n\n1.  Converters, control, memory traffic and achieved model quality\n2.  Only the crossbar’s current\n3.  Only the optical propagation time\n\nAnswer and reasoning\n\nConverters, control, memory traffic and achieved model quality\n\nThe complete task needs interfaces and acceptable outputs; excluding them can turn a component result into an unsupported system claim.\n\n## Evidence and scope\n\nThe IBM and Nature sources describe particular research systems. No commercial deployment scale, universal energy advantage or precision equivalence is asserted.\n\nUse the execution investigation for the shared tensor-to-memory-to-result thread; no current standalone calculator models this lesson’s full mechanism.\n\n## Sources\n\n-   [An energy-efficient analog chip for AI inference](https://research.ibm.com/blog/analog-ai-chip-inference)\n-   [Parallel convolutional processing using an integrated photonic tensor core](https://www.nature.com/articles/s41586-020-03070-1)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/analog-photonic-research-3227848746f7ea50.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Multiply–accumulate and fused arithmetic](https://semiaifoundry.com/learn/atlas/mac/)\n-   [Quantization and numerical representation](https://semiaifoundry.com/learn/atlas/quantization/)\n\n### Related lessons\n\n-   [Workload contract and architecture selection](https://semiaifoundry.com/learn/atlas/chip-workload-contract/)"
}