# Full adder and carry network

Canonical: https://semiaifoundry.com/learn/atlas/adder/
Revision: 2026-10-07
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Arithmetic circuits · Atlas v1.3.0

# Full adder and carry network

Combines binary operands and propagates the carry needed for exact integer addition.

[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#adder)Microscopic bit slices forming a larger arithmetic block

Learning objectiveTrace sum and carry bits through a finite-width binary addition and identify unsigned overflow.

## The mechanism

A one-bit full adder accepts two operand bits and a carry input, producing a sum bit and a carry output. Connecting these slices builds wider addition. In a ripple structure, a carry may pass through many consecutive slices before the answer settles. Faster designs compute carry relationships using additional parallel logic, trading more hardware and wiring for reduced depth. The atlas separates sum paths from carry paths so an addition becomes a visible dependency graph rather than a glowing arithmetic box. Signed interpretation, overflow, and finite output width must be specified by the surrounding architecture. The same physical logic can participate in data arithmetic, addresses, counters, and control decisions.

1.  Combine each pair of operand bits with the incoming carry condition.
2.  Generate a sum bit and a carry relationship for the next position.
3.  Propagate or compute those carry relationships across the chosen word width.

## Science and assumptions

### Generate and propagate

$$
G_i=A_i\land B_i,\quad P_i=A_i\oplus B_i,\quad C_{i+1}=G_i\lor(P_i\land C_i)
$$

A position generates a carry when both operand bits are one. It propagates the incoming carry when their XOR is one. Outgoing carry is generate OR propagate-AND-incoming-carry.

Symbols and units

Aᵢ

First operand bit at position i

Boolean

Bᵢ

Second operand bit at position i

Boolean

Gᵢ

Carry-generate bit

Boolean

Pᵢ

Carry-propagate bit under XOR convention

Boolean

Cᵢ

Incoming carry bit

Boolean

Cᵢ₊₁

Outgoing carry bit

Boolean

i

Bit-position index

integer index

A bit position either generates a carry or propagates the incoming one. Expanding these relations lets a wider adder compute carry conditions with less serial ripple depth.

Assumptions Boolean arithmetic with juxtaposition as AND; delay and wiring costs depend on the chosen physical carry network.

## Engineering example

Worked four-bit addition: 0111₂ + 0011₂ = 1010₂, or 7 + 3 = 10. For 1111₂ + 0001₂, the stored four-bit sum is 0000₂ and carry-out is 1; discarding that carry changes the represented unsigned result from 16 to 0.

## Distinctions and tradeoffs

A carry network is a physical dependency path; writing a plus sign does not make a wide addition instantaneous.

Parallel carry logic reduces depth. It adds routing and cell overhead.

Addition combines partial products and accumulations. It also supports the address and control work around matrix operations.

## Specifications and interfaces

One-bit inputs

A, B, carry-in

Three input bits.

Sum equation

S = A XOR B XOR Cin

Exact Boolean relation.

Carry equation

Cout = AB + ACin + BCin

Plus denotes Boolean OR.

### Interfaces

Operands and carry Input

Binary bit vectors

Sum and carry Output

Integer addition result

## Check your understanding

### Why use more elaborate carry logic?

1.  To reduce the depth of carry dependencies
2.  To remove the need to represent input numbers
3.  To make every adder an analog memory

Answer and reasoning

To reduce the depth of carry dependencies

Parallel carry computation can shorten the waiting path, usually at additional area and routing cost.

## Evidence and scope

The carry relations follow the linked digital-design lecture. Examples are unsigned four-bit arithmetic; signed overflow is a different condition, and gate delay is outside the truth-table calculation.

Inspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network.

## Sources

-   [University of Washington CSE 370 — Adders](https://courses.cs.washington.edu/courses/cse370/08au/Lecture%20Slides/Lec14-Adders.pdf)

[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/adder-b13c5aa2d36b257c.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)

## Continue exploring

### Foundations

-   [Two-input CMOS NAND gate](https://semiaifoundry.com/learn/atlas/nand/)

### Related lessons

-   [Binary multiplier and partial-product reduction](https://semiaifoundry.com/learn/atlas/multiplier/)
-   [Multiply–accumulate and fused arithmetic](https://semiaifoundry.com/learn/atlas/mac/)
-   [Edge-triggered D flip-flop](https://semiaifoundry.com/learn/atlas/flipflop/)