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      "title": "University of Washington CSE 370 — Adders",
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  "content": "Arithmetic circuits · Atlas v1.3.0\n\n# Full adder and carry network\n\nCombines binary operands and propagates the carry needed for exact integer addition.\n\n[Explore in Atlas](https://semiaifoundry.com/ai-atlas/#adder)Microscopic bit slices forming a larger arithmetic block\n\nLearning objectiveTrace sum and carry bits through a finite-width binary addition and identify unsigned overflow.\n\n## The mechanism\n\nA one-bit full adder accepts two operand bits and a carry input, producing a sum bit and a carry output. Connecting these slices builds wider addition. In a ripple structure, a carry may pass through many consecutive slices before the answer settles. Faster designs compute carry relationships using additional parallel logic, trading more hardware and wiring for reduced depth. The atlas separates sum paths from carry paths so an addition becomes a visible dependency graph rather than a glowing arithmetic box. Signed interpretation, overflow, and finite output width must be specified by the surrounding architecture. The same physical logic can participate in data arithmetic, addresses, counters, and control decisions.\n\n1.  Combine each pair of operand bits with the incoming carry condition.\n2.  Generate a sum bit and a carry relationship for the next position.\n3.  Propagate or compute those carry relationships across the chosen word width.\n\n## Science and assumptions\n\n### Generate and propagate\n\n$$\nG_i=A_i\\land B_i,\\quad P_i=A_i\\oplus B_i,\\quad C_{i+1}=G_i\\lor(P_i\\land C_i)\n$$\n\nA position generates a carry when both operand bits are one. It propagates the incoming carry when their XOR is one. Outgoing carry is generate OR propagate-AND-incoming-carry.\n\nSymbols and units\n\nAᵢ\n\nFirst operand bit at position i\n\nBoolean\n\nBᵢ\n\nSecond operand bit at position i\n\nBoolean\n\nGᵢ\n\nCarry-generate bit\n\nBoolean\n\nPᵢ\n\nCarry-propagate bit under XOR convention\n\nBoolean\n\nCᵢ\n\nIncoming carry bit\n\nBoolean\n\nCᵢ₊₁\n\nOutgoing carry bit\n\nBoolean\n\ni\n\nBit-position index\n\ninteger index\n\nA bit position either generates a carry or propagates the incoming one. Expanding these relations lets a wider adder compute carry conditions with less serial ripple depth.\n\nAssumptions Boolean arithmetic with juxtaposition as AND; delay and wiring costs depend on the chosen physical carry network.\n\n## Engineering example\n\nWorked four-bit addition: 0111₂ + 0011₂ = 1010₂, or 7 + 3 = 10. For 1111₂ + 0001₂, the stored four-bit sum is 0000₂ and carry-out is 1; discarding that carry changes the represented unsigned result from 16 to 0.\n\n## Distinctions and tradeoffs\n\nA carry network is a physical dependency path; writing a plus sign does not make a wide addition instantaneous.\n\nParallel carry logic reduces depth. It adds routing and cell overhead.\n\nAddition combines partial products and accumulations. It also supports the address and control work around matrix operations.\n\n## Specifications and interfaces\n\nOne-bit inputs\n\nA, B, carry-in\n\nThree input bits.\n\nSum equation\n\nS = A XOR B XOR Cin\n\nExact Boolean relation.\n\nCarry equation\n\nCout = AB + ACin + BCin\n\nPlus denotes Boolean OR.\n\n### Interfaces\n\nOperands and carry Input\n\nBinary bit vectors\n\nSum and carry Output\n\nInteger addition result\n\n## Check your understanding\n\n### Why use more elaborate carry logic?\n\n1.  To reduce the depth of carry dependencies\n2.  To remove the need to represent input numbers\n3.  To make every adder an analog memory\n\nAnswer and reasoning\n\nTo reduce the depth of carry dependencies\n\nParallel carry computation can shorten the waiting path, usually at additional area and routing cost.\n\n## Evidence and scope\n\nThe carry relations follow the linked digital-design lecture. Examples are unsigned four-bit arithmetic; signed overflow is a different condition, and gate delay is outside the truth-table calculation.\n\nInspect row–column products and accumulated results in a small integer matrix; this does not simulate the individual gate network.\n\n## Sources\n\n-   [University of Washington CSE 370 — Adders](https://courses.cs.washington.edu/courses/cse370/08au/Lecture%20Slides/Lec14-Adders.pdf)\n\n[Published lesson data](https://semiaifoundry.com/ai-atlas/lesson-data/adder-b13c5aa2d36b257c.json) · [Atlas releases and licensing](https://semiaifoundry.com/ai-atlas/licenses.html)\n\n## Continue exploring\n\n### Foundations\n\n-   [Two-input CMOS NAND gate](https://semiaifoundry.com/learn/atlas/nand/)\n\n### Related lessons\n\n-   [Binary multiplier and partial-product reduction](https://semiaifoundry.com/learn/atlas/multiplier/)\n-   [Multiply–accumulate and fused arithmetic](https://semiaifoundry.com/learn/atlas/mac/)\n-   [Edge-triggered D flip-flop](https://semiaifoundry.com/learn/atlas/flipflop/)"
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